615 lines
21 KiB
Scala
615 lines
21 KiB
Scala
package freechips.rocketchip.tilelink
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import chisel3._
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import chisel3.util._
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import chisel3.experimental._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import org.chipsalliance.cde.config.{Parameters, Field}
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case object VortexL1Key extends Field[Option[VortexL1Config]](None /*default*/ )
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case class VortexL1Config(
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numBanks: Int,
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wordSize: Int, // This is the read/write granularity of the L1 cache
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cacheLineSize: Int,
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coreTagWidth: Int,
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writeInfoReqQSize: Int,
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mshrSize: Int,
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memSideSourceIds: Int,
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uncachedAddrSets: Seq[AddressSet]
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) {
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def coreTagPlusSizeWidth: Int = {
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log2Ceil(wordSize) + coreTagWidth
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}
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// NOTE: This assertion depends on the fact that the Vortex cache is
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// configured to have 1 bank, and that it uses MSHR id as the tag of
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// memory-side requests. Otherwise, it will append bank id to the tag as
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// well and break this requirement.
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require(
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mshrSize == memSideSourceIds,
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"MSHR size must match the number of sourceIds to downstream."
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)
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}
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object defaultVortexL1Config
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extends VortexL1Config(
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numBanks = 4,
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wordSize = 16,
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cacheLineSize = 16,
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coreTagWidth = 8,
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writeInfoReqQSize = 16,
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mshrSize = 8,
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memSideSourceIds = 8,
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// Don't cache CLINT region to ensure coherent access
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uncachedAddrSets = Seq(AddressSet(0x2000000L, 0xffffL))
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)
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class VortexL1Cache(config: VortexL1Config)(implicit p: Parameters)
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extends LazyModule {
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val banks = Seq.tabulate(config.numBanks) { bankId =>
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// helps with name mangling in Verilog
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val bank = LazyModule(new VortexBank(config, bankId))
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bank
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}
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// passthrough
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val passThrough = LazyModule(new VortexBankPassThrough(config))
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// visibility node that exposes to upstream
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val coresideNode = TLIdentityNode()
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// core-side crossbar that arbitrates core requests to banks
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protected val bankXbar = LazyModule(new TLXbar)
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bankXbar.node :=* coresideNode
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banks.foreach { _.coresideNode :=* bankXbar.node }
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passThrough.coresideNode :=* bankXbar.node
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// master node that exposes to and drives the downstream
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val masterNode = TLIdentityNode()
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banks.foreach { masterNode := _.vxCacheToL2Node }
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masterNode := passThrough.vxCacheToL2Node
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lazy val module = new LazyModuleImp(this)
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}
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// TODO: Make this a Blocking Module
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class VortexBankPassThrough(config: VortexL1Config)(implicit p: Parameters)
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extends LazyModule {
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// Slave node to upstream
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val managerParam = Seq(
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TLSlavePortParameters.v1(
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beatBytes = config.wordSize,
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managers = Seq(
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TLSlaveParameters.v1(
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address = config.uncachedAddrSets,
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regionType = RegionType.IDEMPOTENT,
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executable = false,
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supportsGet = TransferSizes(1, config.wordSize),
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supportsPutPartial = TransferSizes(1, config.wordSize),
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supportsPutFull = TransferSizes(1, config.wordSize),
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fifoId = Some(0)
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)
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)
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)
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)
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// Master node to downstream
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val clientParam = Seq(
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TLMasterPortParameters.v1(
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clients = Seq(
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TLMasterParameters.v1(
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name = "VortexBank",
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sourceId = IdRange(
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0,
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1 << (log2Ceil(
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config.memSideSourceIds
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) + 5 /*FIXME: give more sourceId so that passthrough doesn't block; hacky*/ )
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),
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supportsProbe = TransferSizes(1, config.wordSize),
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supportsGet = TransferSizes(1, config.wordSize),
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supportsPutFull = TransferSizes(1, config.wordSize),
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supportsPutPartial = TransferSizes(1, config.wordSize)
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)
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)
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)
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)
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val coresideNode = TLManagerNode(managerParam)
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val vxCacheFetchNode = TLClientNode(clientParam)
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val vxCacheToL2Node = TLIdentityNode()
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vxCacheToL2Node := TLWidthWidget(config.cacheLineSize) := vxCacheFetchNode
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// passthrough logic
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lazy val module = new LazyModuleImp(this) {
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val (upstream, _) = coresideNode.in(0)
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val (downstream, _) = vxCacheFetchNode.out(0)
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downstream.a <> upstream.a
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upstream.d <> downstream.d
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}
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}
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class VortexBank(
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config: VortexL1Config,
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bankId: Int,
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)(implicit p: Parameters)
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extends LazyModule {
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// Generate AddressSet by excluding Addr we don't want
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def generateAddressSets(): Seq[AddressSet] = {
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// suppose have 4 bank
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// base for bank 1: ...000000|01|0000
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// mask for bank 1; 111111|00|1111
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val mask = 0xffffffffL ^ ((config.numBanks - 1) * config.wordSize)
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val base = 0x00000000L | (bankId * config.wordSize)
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val excludeSets = config.uncachedAddrSets
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var remainingSets: Seq[AddressSet] = Seq(AddressSet(base, mask))
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for (excludeSet <- excludeSets) {
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remainingSets = remainingSets.flatMap(_.subtract(excludeSet))
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}
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remainingSets
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}
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// Slave node to upstream
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val managerParam = Seq(
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TLSlavePortParameters.v1(
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beatBytes = config.wordSize,
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managers = Seq(
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TLSlaveParameters.v1(
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address = generateAddressSets(),
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regionType = RegionType.IDEMPOTENT, // idk what this does
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executable = false,
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supportsGet = TransferSizes(1, config.wordSize),
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supportsPutPartial = TransferSizes(1, config.wordSize),
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supportsPutFull = TransferSizes(1, config.wordSize),
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fifoId = Some(0)
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)
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)
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)
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)
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// Master node to downstream
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val clientParam = Seq(
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TLMasterPortParameters.v1(
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clients = Seq(
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TLMasterParameters.v1(
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name = "VortexBank",
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sourceId = IdRange(0, config.memSideSourceIds),
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supportsProbe = TransferSizes(1, config.wordSize),
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supportsGet = TransferSizes(1, config.wordSize),
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supportsPutFull = TransferSizes(1, config.wordSize),
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supportsPutPartial = TransferSizes(1, config.wordSize)
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)
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)
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)
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)
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// Core -> VxCache
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val coresideNode = TLManagerNode(managerParam)
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val vxCacheToL2Node = TLIdentityNode()
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val vxCacheFetchNode = TLClientNode(clientParam)
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// We need this widthWidget here, because whenever the bank is performing
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// read and write to Mem, it must have the illusion that dataWidth is as big
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// as as its cacheline size
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vxCacheToL2Node := TLWidthWidget(config.cacheLineSize) := vxCacheFetchNode
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lazy val module = new VortexBankImp(this, config);
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}
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class VortexBankImp(
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outer: VortexBank,
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config: VortexL1Config
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) extends LazyModuleImp(outer) {
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val vxCache = Module(
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new VX_cache_top(
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WORD_SIZE = config.wordSize,
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CACHE_LINE_SIZE = config.cacheLineSize,
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CORE_TAG_WIDTH = config.coreTagPlusSizeWidth,
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MSHR_SIZE = config.mshrSize
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)
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);
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vxCache.io.clk := clock
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vxCache.io.reset := reset
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val writeReqCount = RegInit(UInt(32.W), 0.U)
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val writeInputFire = Wire(Bool())
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val writeOutputFire = Wire(Bool())
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when(writeInputFire && ~writeOutputFire) {
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writeReqCount := writeReqCount + 1.U
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}.elsewhen(~writeInputFire && writeOutputFire) {
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writeReqCount := writeReqCount - 1.U
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}
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dontTouch(writeInputFire)
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dontTouch(writeOutputFire)
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dontTouch(writeReqCount)
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class WriteReqInfo extends Bundle {
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val id = UInt(32.W)
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val size = UInt(32.W)
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}
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class ReadReqInfo(config: VortexL1Config) extends Bundle {
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val size = UInt(log2Ceil(config.wordSize).W)
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val id = UInt(config.coreTagWidth.W)
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}
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val coreWriteReqQueue = Module(
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new Queue(
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(new WriteReqInfo).cloneType,
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config.writeInfoReqQSize,
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true,
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false
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)
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)
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val readReqInfo = Wire(new ReadReqInfo(config))
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// Translate TL request from Coalescer to requests for VX_cache
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def TLReq2VXReq = {
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val (tlInFromCoal, _) = outer.coresideNode.in.head
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// coal -> vxCache
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tlInFromCoal.a.ready :=
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vxCache.io.core_req_ready && coreWriteReqQueue.io.enq.ready // not optimal
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vxCache.io.core_req_valid := tlInFromCoal.a.valid
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// read = 0, write = 1
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vxCache.io.core_req_rw := !(tlInFromCoal.a.bits.opcode === TLMessages.Get)
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// 4 is also hardcoded, it should be log2WordSize
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vxCache.io.core_req_addr := tlInFromCoal.a.bits.address(
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31,
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log2Ceil(config.wordSize)
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)
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vxCache.io.core_req_byteen := tlInFromCoal.a.bits.mask
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vxCache.io.core_req_data := tlInFromCoal.a.bits.data
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// combine size and tag field into one big wire, to put into
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// vxCache.io.core_req_tag
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readReqInfo.id := tlInFromCoal.a.bits.source
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readReqInfo.size := tlInFromCoal.a.bits.size
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// ignore param, size, corrupt
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vxCache.io.core_req_tag := readReqInfo.asTypeOf(vxCache.io.core_req_tag)
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writeInputFire := vxCache.io.core_req_rw && tlInFromCoal.a.fire
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// vxCache -> coal response on channel D
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// ok ... this part is a little tricky, the downstream coalescer requires
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// the L1 cache to send ack and dataAck, this is how coalescer knows when
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// an inflight ID has retired if we don't send ack, the coalescer will run
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// out of IDs, and can't generate new request
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// Optimization: for write requests from upstream (i.e. coalescer), we send
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// back ack as soon as we can without waiting for the actual ack from
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// downstream (i.e. L2).
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//
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// We still need to store these pending core write requests somewhere,
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// because we can't always ack them in the next cycle, ex. when there's a
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// competing read response.
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// FIXME: currently assuming below buffer is never full
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coreWriteReqQueue.io.enq.valid :=
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tlInFromCoal.a.fire && !(tlInFromCoal.a.bits.opcode === TLMessages.Get)
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coreWriteReqQueue.io.enq.bits.id := tlInFromCoal.a.bits.source
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coreWriteReqQueue.io.enq.bits.size := tlInFromCoal.a.bits.size
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// Prioritize ack for any pending reads over write acks in the queue. Don't
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// ack write if vxCache has a current valid response for reads (vxCache
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// response is always for reads.)
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coreWriteReqQueue.io.deq.ready := tlInFromCoal.d.ready && ~vxCache.io.core_rsp_valid
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// handle competition between a pending read ack response and write ack
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// response
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vxCache.io.core_rsp_ready := tlInFromCoal.d.ready
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tlInFromCoal.d.valid := vxCache.io.core_rsp_valid || coreWriteReqQueue.io.deq.valid
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tlInFromCoal.d.bits.source := Mux(
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vxCache.io.core_rsp_valid,
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vxCache.io.core_rsp_tag.asTypeOf(readReqInfo).id,
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coreWriteReqQueue.io.deq.bits.id
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)
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tlInFromCoal.d.bits.opcode := Mux(
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vxCache.io.core_rsp_valid, // always for reads
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TLMessages.AccessAckData,
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TLMessages.AccessAck
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)
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tlInFromCoal.d.bits.size := Mux(
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vxCache.io.core_rsp_valid,
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vxCache.io.core_rsp_tag.asTypeOf(readReqInfo).size,
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coreWriteReqQueue.io.deq.bits.size
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)
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tlInFromCoal.d.bits.param := 0.U
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tlInFromCoal.d.bits.sink := 0.U
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tlInFromCoal.d.bits.denied := false.B
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tlInFromCoal.d.bits.corrupt := false.B
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tlInFromCoal.d.bits.data := vxCache.io.core_rsp_data
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}
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// Since Vortex L1 is a write-through cache, it doesn't bookkeep writes in
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// its MSHR and therefore doesn't allocate a new tag id for write requests.
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// We use a separate source ID allocator to solve this.
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val sourceGen = Module(
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new NewSourceGenerator(
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log2Ceil(config.memSideSourceIds),
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metadata = Some(UInt(32.W)),
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ignoreInUse = false
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)
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)
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// Translate VX_cache mem request to a TL request to be sent to L2
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def VXReq2TLReq = {
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val (tlOutToL2, _) = outer.vxCacheFetchNode.out.head
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// vxCache -> downstream L2 request
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vxCache.io.mem_req_ready := tlOutToL2.a.ready && sourceGen.io.id.valid
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tlOutToL2.a.valid := vxCache.io.mem_req_valid && sourceGen.io.id.valid
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sourceGen.io.gen := tlOutToL2.a.fire
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sourceGen.io.meta := vxCache.io.mem_req_tag // save the old read id
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writeOutputFire := tlOutToL2.a.fire && vxCache.io.mem_req_rw
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tlOutToL2.a.bits.opcode := Mux(
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vxCache.io.mem_req_rw,
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Mux(
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vxCache.io.mem_req_byteen.andR,
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TLMessages.PutFullData,
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TLMessages.PutPartialData
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),
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TLMessages.Get
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)
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tlOutToL2.a.bits.address := Cat(vxCache.io.mem_req_addr, 0.U(4.W))
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tlOutToL2.a.bits.mask := Mux(
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vxCache.io.mem_req_rw,
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vxCache.io.mem_req_byteen,
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0xffff.U
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)
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tlOutToL2.a.bits.data := vxCache.io.mem_req_data
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tlOutToL2.a.bits.source := sourceGen.io.id.bits
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// ignore param, size, corrupt fields
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tlOutToL2.a.bits.param := 0.U
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tlOutToL2.a.bits.size := 4.U // FIXME: hardcoded
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tlOutToL2.a.bits.corrupt := false.B
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// downstream L2 -> vxCache response
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tlOutToL2.d.ready := vxCache.io.mem_rsp_ready
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vxCache.io.mem_rsp_valid :=
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tlOutToL2.d.valid && (tlOutToL2.d.bits.opcode === TLMessages.AccessAckData)
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vxCache.io.mem_rsp_tag := sourceGen.io.peek
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vxCache.io.mem_rsp_data := tlOutToL2.d.bits.data
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sourceGen.io.reclaim.valid := tlOutToL2.d.fire
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sourceGen.io.reclaim.bits := tlOutToL2.d.bits.source
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}
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TLReq2VXReq
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VXReq2TLReq
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}
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class VX_cache_top(
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// these values should match the default settings in Verilog
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// TODO: INSTANCE_ID
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CACHE_SIZE: Int = 16384 / 4, // <FIXME, divided by 4 for faster simulation
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CACHE_LINE_SIZE: Int = 16,
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NUM_WAYS: Int = 4,
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// for single-bank configuration, set NUM_REQS = 1 and instead set
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// WORD_SIZE to something wider than 4
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WORD_SIZE: Int = 16,
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CRSQ_SIZE: Int = 2,
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MSHR_SIZE: Int = 16,
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MRSQ_SIZE: Int = 0,
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MREQ_SIZE: Int = 4,
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WRITE_ENABLE: Int = 1,
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UUID_WIDTH: Int = 0, // FIXME: should be different for debug
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CORE_TAG_WIDTH: Int =
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16, // source ID ranges from 0 to 1 << 10, we need to allocate upper bits to save size
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CORE_OUT_REG : Int = 0,
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MEM_OUT_REG : Int = 0,
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) extends BlackBox(
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Map(
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// NOTE: NUM_REQS is analogous to SIMD width, whereas NUM_BANKS is the
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// actual number of banks. VX_cache.sv instantiates VX_stream_xbar
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// that arbitrates the higher NUM_REQS into NUM_BANKS. Since we do
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// that logic ourselves using TL units, fix those params to 1 for the
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// Verilog side.
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"NUM_REQS" -> 1,
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"CACHE_SIZE" -> CACHE_SIZE,
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"LINE_SIZE" -> CACHE_LINE_SIZE,
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// NUM_BANKS is set to 1 to treat a whole VX_cache_top instance as a
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// single bank
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"NUM_BANKS" -> 1,
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"NUM_WAYS" -> NUM_WAYS,
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"WORD_SIZE" -> WORD_SIZE,
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"CRSQ_SIZE" -> CRSQ_SIZE,
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"MSHR_SIZE" -> MSHR_SIZE,
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"MRSQ_SIZE" -> MRSQ_SIZE,
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"MREQ_SIZE" -> MREQ_SIZE,
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"WRITE_ENABLE" -> WRITE_ENABLE,
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"UUID_WIDTH" -> UUID_WIDTH,
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"TAG_WIDTH" -> CORE_TAG_WIDTH,
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"CORE_OUT_REG" -> CORE_OUT_REG,
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"MEM_OUT_REG" -> MEM_OUT_REG,
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// Although VX_cache_top exposes it as a parameter, MEM_TAG_WIDTH is
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// not really configurable -- it is set to be a concatenation of the
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// MSHR id and cache bank id. Instead of trying to configure it from
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// Chisel side, we try to figure out its value that's elaborated in the
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// Verilog side and configure the Chisel io width correspondingly.
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// "MEM_TAG_WIDTH" -> MEM_TAG_WIDTH
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)
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)
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with HasBlackBoxResource {
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def memTagWidth(mshrSize: Int, numBanks: Int): Int =
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log2Ceil(mshrSize) + log2Ceil(numBanks)
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val MEM_TAG_WIDTH = memTagWidth(MSHR_SIZE, 1/* NUM_BANKS */)
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val io = IO(new Bundle {
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val clk = Input(Clock())
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val reset = Input(Reset())
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// CACHE <> CORE
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val core_req_valid = Input(Bool())
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val core_req_rw = Input(Bool())
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val core_req_byteen = Input(UInt(WORD_SIZE.W))
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val core_req_addr = Input(UInt(WORD_ADDR_WIDTH.W))
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val core_req_data = Input(UInt((WORD_SIZE * 8).W))
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val core_req_tag = Input(UInt(CORE_TAG_WIDTH.W))
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val core_req_ready = Output(Bool())
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val core_rsp_valid = Output(Bool()) // 1 bit wide
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val core_rsp_data = Output(UInt((WORD_SIZE * 8).W))
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val core_rsp_tag = Output(UInt(CORE_TAG_WIDTH.W))
|
|
val core_rsp_ready = Input(Bool())
|
|
|
|
// CACHE <> L2
|
|
val mem_req_valid = Output(Bool())
|
|
val mem_req_rw = Output(Bool())
|
|
val mem_req_byteen = Output(UInt(CACHE_LINE_SIZE.W))
|
|
val mem_req_addr = Output(UInt(MEM_ADDR_WIDTH.W))
|
|
val mem_req_data = Output(UInt((CACHE_LINE_SIZE * 8).W))
|
|
val mem_req_tag = Output(UInt(MEM_TAG_WIDTH.W))
|
|
val mem_req_ready = Input(Bool())
|
|
|
|
val mem_rsp_valid = Input(Bool())
|
|
val mem_rsp_data = Input(UInt((CACHE_LINE_SIZE * 8).W))
|
|
val mem_rsp_tag = Input(UInt(MEM_TAG_WIDTH.W))
|
|
val mem_rsp_ready = Output(Bool())
|
|
})
|
|
|
|
addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_bank.sv")
|
|
// addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_bypass.sv")
|
|
addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_data.sv")
|
|
addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_define.vh")
|
|
addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_init.sv")
|
|
addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_mshr.sv")
|
|
addResource("/vsrc/vortex/hw/rtl/cache/VX_cache.sv")
|
|
addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_tags.sv")
|
|
addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_top.sv")
|
|
}
|
|
|
|
// <FIXME> Delete the following NewSourceGenerator when merging with origin/graphics
|
|
// we should just use the one in coalescing.scala written by hansung
|
|
|
|
class NewSourceGenerator[T <: Data](
|
|
sourceWidth: Int,
|
|
metadata: Option[T] = None,
|
|
ignoreInUse: Boolean = false
|
|
) extends Module {
|
|
def getMetadataType = metadata match {
|
|
case Some(gen) => gen.cloneType
|
|
case None => UInt(0.W)
|
|
}
|
|
val io = IO(new Bundle {
|
|
val gen = Input(Bool())
|
|
val reclaim = Input(Valid(UInt(sourceWidth.W)))
|
|
val id = Output(Valid(UInt(sourceWidth.W)))
|
|
// below are used only when metadata is not None
|
|
// `meta` is used as input when a request succeeds id generation to store
|
|
// its value to the table.
|
|
// `peek` is the retrieved metadata saved for the request when corresponding
|
|
// request has come back, setting `reclaim`.
|
|
// Although these do not use ValidIO, it is safe because any in-flight
|
|
// response coming back should have allocated a valid entry in the table
|
|
// when it went out.
|
|
val meta = Input(getMetadataType)
|
|
val peek = Output(getMetadataType)
|
|
// for debugging; indicates whether there is at least one inflight request
|
|
// that hasn't been reclaimed yet
|
|
val inflight = Output(Bool())
|
|
})
|
|
val head = RegInit(UInt(sourceWidth.W), 0.U)
|
|
head := Mux(io.gen, head + 1.U, head)
|
|
|
|
val outstanding = RegInit(UInt((sourceWidth + 1).W), 0.U)
|
|
io.inflight := (outstanding > 0.U) || io.gen
|
|
|
|
val numSourceId = 1 << sourceWidth
|
|
val row = new Bundle {
|
|
val meta = getMetadataType
|
|
val id = Valid(UInt(sourceWidth.W))
|
|
val age = UInt(32.W) // New age field for debugging
|
|
}
|
|
// valid: in use, invalid: available
|
|
// val occupancyTable = Mem(numSourceId, Valid(UInt(sourceWidth.W)))
|
|
val occupancyTable = Mem(numSourceId, row)
|
|
when(reset.asBool) {
|
|
(0 until numSourceId).foreach { i =>
|
|
occupancyTable(i).id.valid := false.B
|
|
occupancyTable(i).age := 0.U // Reset age during reset
|
|
}
|
|
}
|
|
val frees = (0 until numSourceId).map(!occupancyTable(_).id.valid)
|
|
val lowestFree = PriorityEncoder(frees)
|
|
val lowestFreeRow = occupancyTable(lowestFree)
|
|
|
|
io.id.valid := (if (ignoreInUse) true.B else !lowestFreeRow.id.valid)
|
|
io.id.bits := lowestFree
|
|
when(io.gen && io.id.valid /* fire */ ) {
|
|
occupancyTable(io.id.bits).id.valid := true.B // mark in use
|
|
occupancyTable(
|
|
io.id.bits
|
|
).age := 0.U // reset age upon issuing, double safety
|
|
if (metadata.isDefined) {
|
|
occupancyTable(io.id.bits).meta := io.meta
|
|
}
|
|
}
|
|
|
|
// Increase age of all inflight IDs by 1, except for the one being reclaimed
|
|
for (i <- 0 until numSourceId) {
|
|
when(
|
|
occupancyTable(
|
|
i
|
|
).id.valid && (i.U =/= io.reclaim.bits || !io.reclaim.valid)
|
|
) {
|
|
occupancyTable(i).age := occupancyTable(i).age + 1.U
|
|
}
|
|
}
|
|
|
|
when(io.reclaim.valid) {
|
|
assert(
|
|
occupancyTable(io.reclaim.bits).id.valid === true.B,
|
|
"tried to reclaim a non-used id"
|
|
)
|
|
occupancyTable(io.reclaim.bits).id.valid := false.B // mark freed
|
|
occupancyTable(io.reclaim.bits).age := 0.U
|
|
}
|
|
|
|
io.peek := {
|
|
if (metadata.isDefined) occupancyTable(io.reclaim.bits).meta else 0.U
|
|
}
|
|
|
|
when(io.gen && io.id.valid) {
|
|
when(!io.reclaim.valid) {
|
|
assert(outstanding < (1 << sourceWidth).U)
|
|
outstanding := outstanding + 1.U
|
|
}
|
|
}.elsewhen(io.reclaim.valid) {
|
|
assert(outstanding > 0.U)
|
|
outstanding := outstanding - 1.U
|
|
}
|
|
|
|
// Debugging wires
|
|
val ages = VecInit((0 until numSourceId).map(i => occupancyTable(i).age))
|
|
val oldestIndex = PriorityEncoder(
|
|
ages.map(a => a === ages.reduce((x, y) => Mux(x > y, x, y)))
|
|
)
|
|
val oldestIdInflight = Wire(UInt(sourceWidth.W))
|
|
val oldestMetadata = Wire(getMetadataType)
|
|
val oldestAge = Wire(UInt(32.W))
|
|
|
|
oldestIdInflight := oldestIndex
|
|
oldestMetadata := occupancyTable(oldestIndex).meta
|
|
oldestAge := occupancyTable(oldestIndex).age
|
|
assert(
|
|
oldestAge <= 2000.U,
|
|
"One id in the SourceGen is not released for long time, potential bug !"
|
|
)
|
|
|
|
dontTouch(oldestIdInflight)
|
|
dontTouch(oldestMetadata)
|
|
dontTouch(oldestAge)
|
|
dontTouch(outstanding)
|
|
|
|
}
|