Hansung Kim
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dca52ace0b
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Fix verilog lint error
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2023-04-10 20:37:26 -07:00 |
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Hansung Kim
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9bfb813e1b
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Thread -> Lane
"thread" is confusing, unify to lane when denoting a hardware SIMD lane
inside a single warp.
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2023-03-09 22:09:21 -08:00 |
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Vamber Yang
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0de09daa05
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MemTracer able to read and write according to trace file, also support thread_id skipping in trace file
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2023-03-08 17:34:10 -08:00 |
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Hansung Kim
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db9be56191
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Properly connect each lane to TL node
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2023-03-05 00:18:29 -08:00 |
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Hansung Kim
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5f55a7578f
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Recover lost changes
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2023-03-03 22:36:54 -08:00 |
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Hansung Kim
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9025729c0e
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Emit address in addition to cycle
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2023-02-27 17:36:54 -08:00 |
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Hansung Kim
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0ebaed5f1b
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Communicate trace cycle data from C++ to Chisel
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2023-02-27 14:40:49 -08:00 |
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Hansung Kim
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72de4bca66
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Initial parsing of memory trace file in C++
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2023-02-27 13:47:30 -08:00 |
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Hansung Kim
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80e4b5c734
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Set up simple DPI for trace-driven testing
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2023-02-26 20:39:19 -08:00 |
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