Hansung Kim
dca52ace0b
Fix verilog lint error
2023-04-10 20:37:26 -07:00
Hansung Kim
b53711965e
Connect TL edge data to SimMemTraceLogger
...
TODO: since TileLink rounds all address down to a multiple of its beat
size (8 in the current code), we can't directly compare the memory trace
input to its output. Need to take masks into account.
2023-04-10 20:24:27 -07:00
Hansung Kim
af29acdcda
Placeholder for MemTraceLogger C++ code
2023-04-09 14:53:02 -07:00
Vamber Yang
8e5254292b
Attach MemTracer to SBus , all physical addr hashed between 0X80000000->0X90000000
2023-04-05 23:43:22 -07:00
Hansung Kim
bdc32b765f
Accept memory trace filename from VCS plusargs
...
Now can use `EXTRA_SIM_FLAGS="+memtracefile=<tracefile>"` to simulate
with different trace files without recompiling.
2023-04-03 17:41:47 -07:00
Hansung Kim
9bfb813e1b
Thread -> Lane
...
"thread" is confusing, unify to lane when denoting a hardware SIMD lane
inside a single warp.
2023-03-09 22:09:21 -08:00
Vamber Yang
0de09daa05
MemTracer able to read and write according to trace file, also support thread_id skipping in trace file
2023-03-08 17:34:10 -08:00
Hansung Kim
41ecf6bc20
Squelch debug prints in SimMemTrace
2023-03-07 17:53:09 -08:00
Hansung Kim
db9be56191
Properly connect each lane to TL node
2023-03-05 00:18:29 -08:00
Hansung Kim
172ab51355
Fix formatting and unused warnings
2023-03-03 23:44:50 -08:00
Hansung Kim
5f55a7578f
Recover lost changes
2023-03-03 22:36:54 -08:00
Hansung Kim
dcb49f7683
Doc update
2023-03-03 21:22:56 -08:00
Hansung Kim
9025729c0e
Emit address in addition to cycle
2023-02-27 17:36:54 -08:00
Hansung Kim
0ebaed5f1b
Communicate trace cycle data from C++ to Chisel
2023-02-27 14:40:49 -08:00
Hansung Kim
72de4bca66
Initial parsing of memory trace file in C++
2023-02-27 13:47:30 -08:00
Hansung Kim
80e4b5c734
Set up simple DPI for trace-driven testing
2023-02-26 20:39:19 -08:00
