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Decrease imemSourceWidth to 4

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Hansung Kim
2024-01-18 22:16:22 -08:00
parent 0fd4d0a76f
commit fec3d61dd6
1 changed files with 1 additions and 1 deletions
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src/main/scala/radiance/tile/VortexTile.scala
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@@ -171,7 +171,7 @@ class VortexTile private (
// ibuffer size is set as a hardcoded macro IBUF_SIZE that's uncontrollable // ibuffer size is set as a hardcoded macro IBUF_SIZE that's uncontrollable
// from Chisel, there's no easy solution. We at least don't expose this as a // from Chisel, there's no easy solution. We at least don't expose this as a
// Parameter and leave as a hardcoded value here. // Parameter and leave as a hardcoded value here.
val imemSourceWidth = 6 // 1 << imemSourceWidth == IBUF_SIZE val imemSourceWidth = 4 // 1 << imemSourceWidth == IBUF_SIZE
val dmemSourceWidth = p(SIMTCoreKey) match { val dmemSourceWidth = p(SIMTCoreKey) match {
// TODO: respect coalescer newSrcIds // TODO: respect coalescer newSrcIds