From fec3d61dd64db66b3a7d4916bad8f4c2e62cf57a Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Thu, 18 Jan 2024 22:16:22 -0800 Subject: [PATCH] Decrease imemSourceWidth to 4 --- src/main/scala/radiance/tile/VortexTile.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/radiance/tile/VortexTile.scala b/src/main/scala/radiance/tile/VortexTile.scala index 37439dc..10d09c1 100644 --- a/src/main/scala/radiance/tile/VortexTile.scala +++ b/src/main/scala/radiance/tile/VortexTile.scala @@ -171,7 +171,7 @@ class VortexTile private ( // ibuffer size is set as a hardcoded macro IBUF_SIZE that's uncontrollable // from Chisel, there's no easy solution. We at least don't expose this as a // Parameter and leave as a hardcoded value here. - val imemSourceWidth = 6 // 1 << imemSourceWidth == IBUF_SIZE + val imemSourceWidth = 4 // 1 << imemSourceWidth == IBUF_SIZE val dmemSourceWidth = p(SIMTCoreKey) match { // TODO: respect coalescer newSrcIds