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Properly handle upstream and downstream backpressure for respQueues

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This commit is contained in:
Hansung Kim
2023-10-24 11:36:18 -07:00
parent 8e0904a1ad
commit e9c206dfa2
2 changed files with 23 additions and 21 deletions
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11
src/main/scala/tile/VortexTile.scala
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@@ -216,7 +216,7 @@ class VortexTile private (
// Conditionally instantiate memory coalescer
val coalescerNode = p(CoalescerKey) match {
case Some(coalescerParam) => {
val coal = LazyModule(new CoalescingUnit(coalescerParam.copy(enable = false)))
val coal = LazyModule(new CoalescingUnit(coalescerParam.copy(enable = true)))
coal.cpuNode :=* dmemAggregateNode
coal.aggregateNode // N+1 lanes
}
@@ -407,11 +407,10 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
val matchingSources = Wire(UInt(outer.numLanes.W))
matchingSources := dmemTLBundles
.map(b =>
// If there is no valid response across all lanes, matchingSources
// should always be 1, or otherwise downstream would think upstream
// is blocked and re-try sending
!arb.io.out.valid
|| (b.d.bits.source === arb.io.out.bits))
// If there is no valid response pending across all lanes,
// matchingSources should not filter out upstream ready signals, so
// set it to all-1
!arb.io.out.valid || (b.d.bits.source === arb.io.out.bits))
.asUInt
// connection: VortexBundle <--> VortexTLAdapter <--> dmemNodes