Fake tensor core at RadianceTile for Verilog unique-ification

src/main/scala/radiance/tile/RadianceTile.scala

@@ -379,6 +379,12 @@ class RadianceTile private (
     tlMasterXbar.node :=* AddressOrNode(base) :=* dcacheNode
   }
 
+  // Instantiate a fake TensorCoreDecoupled module to force unique-ification of
+  // module names in the Chisel-generated Verilog.  This should be disabled for
+  // synthesis runs
+  val tensor = LazyModule(new radiance.core.TensorCoreDecoupledTL)
+  tlMasterXbar.node :=* tensor.node
+
   /* below are copied from rocket */
 
   val tile_master_blocker =
@@ -839,6 +845,10 @@ class RadianceTileModuleImp(outer: RadianceTile)
   // TODO: generalize for useVxCache
   if (!outer.radianceParams.useVxCache) {}
 
+  // connect io.start and io.finish of the fake TensorCoreDecoupled module to
+  // prevent optimize-out
+  outer.tensor.module.io.start := true.B
+
   // // RoCC
   // if (outer.roccs.size > 0) {
   //   val (respArb, cmdRouter) = {

src/main/scala/radiance/tile/VortexCore.scala

@@ -242,8 +242,6 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
   // addResource("/vsrc/vortex/hw/rtl/mem/VX_gbar_arb.sv")
   // addResource("/vsrc/vortex/hw/rtl/mem/VX_gbar_unit.sv")
 
-  addResource("/vsrc/vortex/hw/rtl/mem/VX_tc_bus_if.sv")
-
   addResource("/vsrc/vortex/hw/rtl/libs/VX_allocator.sv")
   // addResource("/vsrc/vortex/hw/rtl/libs/VX_avs_adapter.sv")
   // addResource("/vsrc/vortex/hw/rtl/libs/VX_axi_adapter.sv")
@@ -408,6 +406,7 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
   // tensor core
   addResource("/vsrc/vortex/hw/rtl/core/VX_tensor_core.sv")
   addResource("/vsrc/vortex/hw/rtl/core/VX_tensor_hopper_core.sv")
+  addResource("/vsrc/vortex/hw/rtl/mem/VX_tc_bus_if.sv")
 //  addResource("/vsrc/vortex/hw/rtl/core/VX_tensor_ucode.vh")
   addResource("/vsrc/vortex/hw/rtl/core/VX_uop_sequencer.sv")
   addResource("/vsrc/vortex/hw/rtl/core/VX_reduce_unit.sv")