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VX_FatBank runs in SoC Config with Coalescer till termination

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Issues addressed:
1. FatBank ack to downstream coalescer with the correct size on ChannelD
2. FatBank ack to downstream coalescer immediately after W Req
3. FatBank generates unique ID for W Req to L2
4. Allows coalescer to config max Coal to L1 ReadSize at compile time

Ungoing issues:
1. Magic Number
2. Verification
3. Multi-Bank Integration
This commit is contained in:
Vamber Yang
2023-10-16 10:31:31 -07:00
parent 127d7613e1
commit e50903ed42
3 changed files with 313 additions and 82 deletions
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35
src/main/scala/tilelink/CanHaveMemtraceCore.scala
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@@ -3,6 +3,8 @@ package freechips.rocketchip.tilelink
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.subsystem.BaseSubsystem
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket
// TODO: possibly move to somewhere closer to CoalescingUnit
// TODO: separate coalescer config from CanHaveMemtraceCore
@@ -44,16 +46,39 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
}
case None => tracer.node
}
val upstream = p(CoalXbarKey) match {
val coalXbar = p(CoalXbarKey) match {
case Some(xbarParam) =>{
val priorityXbar = LazyModule(new CoalescerTLPriortyXBar)
println(s"============ Using Priority XBar for Coalescer Requests ")
priorityXbar.node :=* coalescerNode
priorityXbar.node
val coXbar = LazyModule(new TLXbar)
println(s"============ Using TLXBar for Coalescer Requests ")
coXbar.node :=* coalescerNode
coXbar.node
}
case None => coalescerNode
}
val vortexBank = p(VortexFatBankKey) match {
case Some(fatBankParam) =>{
val vx_fatbank = LazyModule(new VortexFatBank(fatBankParam))
println(s"============ Using Vortex FatBank as L1 ")
vx_fatbank.coalToVxCacheNode :=* coalXbar
vx_fatbank.vxCacheToL2Node
}
case None => coalXbar
}
//If there is only 1 bank, the code below is useless
val upstream = p(CoalXbarKey) match {
case Some(xbarParam) =>{
val tileXbar = LazyModule(new TLXbar)
println(s"============ Using TLXBar for L1 Requests ")
tileXbar.node :=* vortexBank
tileXbar.node
}
case None => vortexBank
}
sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
}
}