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Comment out hartid and fpu from VortexBundle

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These are mostly copied from Rocket and we're not sure they're necessary
for Vortex.
This commit is contained in:
Hansung Kim
2023-10-11 20:29:15 -07:00
parent acc66e413a
commit dab1d907d6
2 changed files with 9 additions and 6 deletions
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4
src/main/scala/rocket/VortexCore.scala
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@@ -15,7 +15,7 @@ import tile.VortexTile
class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle {
val clock = Input(Clock())
val reset = Input(Reset())
val hartid = Input(UInt(hartIdLen.W))
// val hartid = Input(UInt(hartIdLen.W))
val reset_vector = Input(UInt(resetVectorLen.W))
val interrupts = Input(new CoreInterrupts())
@@ -33,7 +33,7 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
val d = Flipped(tile.memNode.out.head._1.d.cloneType)
}) else None
val fpu = Flipped(new FPUCoreIO())
// val fpu = Flipped(new FPUCoreIO())
//val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
//val trace = Output(new TraceBundle)
//val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))