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Log source ID in the trace

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This commit is contained in:
Hansung Kim
2023-04-17 18:43:17 -07:00
parent 41d520a991
commit d4a51cfee5
5 changed files with 71 additions and 67 deletions
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6
src/main/resources/csrc/SimMemTrace.h
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@@ -5,10 +5,11 @@
struct MemTraceLine {
bool valid = false;
long cycle = 0;
bool is_store = 0;
int core_id = 0;
int lane_id = 0;
int source = 0;
unsigned long address = 0;
bool is_store = 0;
unsigned long data = 0;
int log_data_size = 0;
};
@@ -50,8 +51,9 @@ extern "C" int memtracelogger_init(int is_response, const char *filename);
extern "C" void memtracelogger_log(int handle,
unsigned char trace_log_valid,
unsigned long trace_log_cycle,
unsigned long trace_log_address,
int trace_log_lane_id,
int trace_log_source,
unsigned long trace_log_address,
unsigned char trace_log_is_store,
int trace_log_size,
unsigned long trace_log_data,

24
src/main/resources/csrc/SimMemTraceLogger.cc
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@@ -35,9 +35,9 @@ MemTraceWriter::~MemTraceWriter() {
}
void MemTraceWriter::write_line_to_trace(const MemTraceLine line) {
fprintf(outfile, "%ld %s %d %d 0x%lx 0x%lx %u\n", line.cycle,
fprintf(outfile, "%ld %s %d %d %d, 0x%lx 0x%lx %u\n", line.cycle,
(line.is_store ? "STORE" : "LOAD"), line.core_id, line.lane_id,
line.address, line.data, (1u << line.log_data_size));
line.source, line.address, line.data, (1u << line.log_data_size));
}
// Returns the "handle" ID for this particular logger instance.
@@ -70,13 +70,16 @@ extern "C" int memtracelogger_init(int is_response, const char *filename) {
// This is used to log both TileLink A and D channels.
// TODO: accept core_id as well
extern "C" void
memtracelogger_log(int handle,
unsigned char trace_log_valid, unsigned long trace_log_cycle,
unsigned long trace_log_address, int trace_log_lane_id,
unsigned char trace_log_is_store, int trace_log_size,
unsigned long trace_log_data,
unsigned char *trace_log_ready) {
extern "C" void memtracelogger_log(int handle,
unsigned char trace_log_valid,
unsigned long trace_log_cycle,
int trace_log_lane_id,
int trace_log_source,
unsigned long trace_log_address,
unsigned char trace_log_is_store,
int trace_log_size,
unsigned long trace_log_data,
unsigned char *trace_log_ready) {
// printf("memtrace_query(cycle=%ld, tid=%d)\n", trace_read_cycle,
// trace_read_lane_id);
*trace_log_ready = 1;
@@ -90,10 +93,11 @@ memtracelogger_log(int handle,
MemTraceLine line{.valid = (trace_log_valid == 1),
.cycle = static_cast<long>(trace_log_cycle),
.is_store = (trace_log_is_store == 1),
.core_id = 0, // TODO support multicores
.lane_id = trace_log_lane_id,
.source = trace_log_source,
.address = trace_log_address,
.is_store = (trace_log_is_store == 1),
.data = trace_log_data,
.log_data_size = trace_log_size};

3
src/main/resources/vsrc/SimMemTrace.v
View File

@@ -15,7 +15,7 @@ import "DPI-C" function void memtrace_query
(
input bit trace_read_ready,
input longint trace_read_cycle,
input int trace_read_tid,
input int trace_read_lane_id,
output bit trace_read_valid,
output longint trace_read_address,
output bit trace_read_is_store,
@@ -32,7 +32,6 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) (
input trace_read_ready,
output [NUM_LANES-1:0] trace_read_valid,
output [`DATA_WIDTH*NUM_LANES-1:0] trace_read_address,
output [NUM_LANES-1:0] trace_read_is_store,
output [`LOGSIZE_WIDTH*NUM_LANES-1:0] trace_read_size,
output [`DATA_WIDTH*NUM_LANES-1:0] trace_read_data,

26
src/main/resources/vsrc/SimMemTraceLogger.v
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@@ -1,6 +1,7 @@
// FIXME hardcoded
`define DATA_WIDTH 64
`define MAX_NUM_LANES 32
`define SOURCEID_WIDTH 32
`define LOGSIZE_WIDTH 32
import "DPI-C" function int memtracelogger_init(
@@ -17,8 +18,9 @@ import "DPI-C" function void memtracelogger_log
input int handle,
input bit trace_log_valid,
input longint trace_log_cycle,
input int trace_log_lane_id,
input int trace_log_source,
input longint trace_log_address,
input int trace_log_tid,
input bit trace_log_is_store,
input int trace_log_size,
input longint trace_log_data,
@@ -29,16 +31,17 @@ module SimMemTraceLogger #(parameter
IS_RESPONSE = 0,
FILENAME = "undefined",
NUM_LANES = 4) (
input clock,
input reset,
input clock,
input reset,
// NOTE: LSB is lane 0
input [NUM_LANES-1:0] trace_log_valid,
input [`DATA_WIDTH*NUM_LANES-1:0] trace_log_address,
input [NUM_LANES-1:0] trace_log_is_store,
input [`LOGSIZE_WIDTH*NUM_LANES-1:0] trace_log_size,
input [`DATA_WIDTH*NUM_LANES-1:0] trace_log_data,
output trace_log_ready
input [NUM_LANES-1:0] trace_log_valid,
input [`SOURCEID_WIDTH*NUM_LANES-1:0] trace_log_source,
input [`DATA_WIDTH*NUM_LANES-1:0] trace_log_address,
input [NUM_LANES-1:0] trace_log_is_store,
input [`LOGSIZE_WIDTH*NUM_LANES-1:0] trace_log_size,
input [`DATA_WIDTH*NUM_LANES-1:0] trace_log_data,
output trace_log_ready
);
int logger_handle;
bit __in_ready;
@@ -51,6 +54,7 @@ module SimMemTraceLogger #(parameter
// wires going into the DPC
wire __valid [NUM_LANES-1:0];
wire [`SOURCEID_WIDTH-1:0] __source [NUM_LANES-1:0];
wire [`DATA_WIDTH-1:0] __address [NUM_LANES-1:0];
wire __is_store [NUM_LANES-1:0];
wire [`LOGSIZE_WIDTH-1:0] __size [NUM_LANES-1:0];
@@ -63,6 +67,7 @@ module SimMemTraceLogger #(parameter
for (g = 0; g < NUM_LANES; g = g + 1) begin
// LSB is lane 0
assign __valid[g] = trace_log_valid[g];
assign __source[g] = trace_log_source[`SOURCEID_WIDTH*(g+1)-1:`SOURCEID_WIDTH*g];
assign __address[g] = trace_log_address[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g];
assign __is_store[g] = trace_log_is_store[g];
assign __size[g] = trace_log_size[`LOGSIZE_WIDTH*(g+1)-1:`LOGSIZE_WIDTH*g];
@@ -87,8 +92,9 @@ module SimMemTraceLogger #(parameter
logger_handle,
__valid[tid],
cycle_counter,
__address[tid],
tid,
__source[tid],
__address[tid],
__is_store[tid],
__size[tid],
__data[tid],