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bump vortex and increase source ids

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This commit is contained in:
Richard Yan
2023-09-11 14:06:08 -07:00
parent 43f95175f1
commit d392d76608
3 changed files with 4 additions and 3 deletions
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2
src/main/resources/vsrc/vortex

Submodule src/main/resources/vsrc/vortex updated: 7d0d38ca6c...633cffa2f3

1
src/main/scala/rocket/VortexCore.scala
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@@ -167,6 +167,7 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_perf_pipeline_if.sv")
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_gpr_rsp_if.sv")
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_cmt_to_csr_if.sv")
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_csr_to_alu_if.sv")
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_ifetch_rsp_if.sv")
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_alu_req_if.sv")
addResource("/vsrc/vortex/hw/rtl/interfaces/VX_csr_req_if.sv")

4
src/main/scala/tile/VortexTile.scala
View File

@@ -90,7 +90,7 @@ class VortexTile private(
val imemNode = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1 << 8), // TODO magic number
sourceId = IdRange(0, 1 << 10), // TODO magic number
name = s"Vortex Core I-Mem",
requestFifo = true,
supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
@@ -100,7 +100,7 @@ class VortexTile private(
val dmemNode = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1 << 8), // TODO magic number
sourceId = IdRange(0, 1 << 10), // TODO magic number
name = s"Vortex Core D-Mem",
requestFifo = true,
supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),