From d392d76608d3dddf90d6e3b146a6bbbeb1c4f2f5 Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Mon, 11 Sep 2023 14:06:08 -0700 Subject: [PATCH] bump vortex and increase source ids --- src/main/resources/vsrc/vortex | 2 +- src/main/scala/rocket/VortexCore.scala | 1 + src/main/scala/tile/VortexTile.scala | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex index 7d0d38c..633cffa 160000 --- a/src/main/resources/vsrc/vortex +++ b/src/main/resources/vsrc/vortex @@ -1 +1 @@ -Subproject commit 7d0d38ca6cafec84bcc720f79a2f18e26222963f +Subproject commit 633cffa2f30b4ef2a5ccbb78ccd1aa1029d6511f diff --git a/src/main/scala/rocket/VortexCore.scala b/src/main/scala/rocket/VortexCore.scala index 813c40f..6949afb 100644 --- a/src/main/scala/rocket/VortexCore.scala +++ b/src/main/scala/rocket/VortexCore.scala @@ -167,6 +167,7 @@ class Vortex(tile: VortexTile)(implicit p: Parameters) addResource("/vsrc/vortex/hw/rtl/interfaces/VX_perf_pipeline_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_gpr_rsp_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_cmt_to_csr_if.sv") + addResource("/vsrc/vortex/hw/rtl/interfaces/VX_csr_to_alu_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_ifetch_rsp_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_alu_req_if.sv") addResource("/vsrc/vortex/hw/rtl/interfaces/VX_csr_req_if.sv") diff --git a/src/main/scala/tile/VortexTile.scala b/src/main/scala/tile/VortexTile.scala index 2bd7574..dfff13b 100644 --- a/src/main/scala/tile/VortexTile.scala +++ b/src/main/scala/tile/VortexTile.scala @@ -90,7 +90,7 @@ class VortexTile private( val imemNode = TLClientNode(Seq(TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( - sourceId = IdRange(0, 1 << 8), // TODO magic number + sourceId = IdRange(0, 1 << 10), // TODO magic number name = s"Vortex Core I-Mem", requestFifo = true, supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes), @@ -100,7 +100,7 @@ class VortexTile private( val dmemNode = TLClientNode(Seq(TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( - sourceId = IdRange(0, 1 << 8), // TODO magic number + sourceId = IdRange(0, 1 << 10), // TODO magic number name = s"Vortex Core D-Mem", requestFifo = true, supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),