Generate explicit clock domain in CanHaveMemtraceCore

src/main/scala/radiance/memory/CanHaveMemtraceCore.scala

@@ -22,6 +22,10 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
       )
     val numLanes = simtParam.nLanes
     val filename = param.tracefilename
+
+    // Need to explicitly generate clock domain; see rocket-chip 8881ccd
+    val memtracerDomain = sbus.generateSynchronousDomain
+    memtracerDomain {
       val tracer = LazyModule(
         new MemTraceDriver(config, filename, param.traceHasSource)(p)
       )
@@ -55,11 +59,8 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
         case None => coalescerNode
       }
 
-    
       val vortexBank = coalXbar
 
-    
-    
       //If there is only 1 bank, the code below is useless
       val upstream = p(CoalXbarKey) match {
         case Some(xbarParam) =>{
@@ -71,7 +72,7 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
         case None => vortexBank
       }
 
-
       sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
     }
+  }
 }