wu-arch/radiance
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

it works

Browse Source
This commit is contained in:
joshua
2023-09-24 17:43:00 -07:00
parent 6a6f7fcaf0
commit c5bfb66ee5
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/tile/VortexTile.scala
View File

@@ -101,7 +101,7 @@ class VortexTile private(
val memNode = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1 << 10), // TODO magic numbers
sourceId = IdRange(0, 1 << 15), // TODO magic numbers
name = s"Vortex Core ${vortexParams.hartId} Mem Interface",
requestFifo = true,
supportsProbe = TransferSizes(16, 16),