From c5bfb66ee523fa7230d129c187b0150c9c42cd1e Mon Sep 17 00:00:00 2001
From: joshua <jyou12@berkeley.edu>
Date: Sun, 24 Sep 2023 17:43:00 -0700
Subject: [PATCH] it works

---
 src/main/scala/tile/VortexTile.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/tile/VortexTile.scala b/src/main/scala/tile/VortexTile.scala
index ac61836..f9d2991 100644
--- a/src/main/scala/tile/VortexTile.scala
+++ b/src/main/scala/tile/VortexTile.scala
@@ -101,7 +101,7 @@ class VortexTile private(
 
   val memNode = TLClientNode(Seq(TLMasterPortParameters.v1(
     clients = Seq(TLMasterParameters.v1(
-      sourceId = IdRange(0, 1 << 10), // TODO magic numbers
+      sourceId = IdRange(0, 1 << 15), // TODO magic numbers
       name = s"Vortex Core ${vortexParams.hartId} Mem Interface",
       requestFifo = true,
       supportsProbe = TransferSizes(16, 16),