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Respect VX_cache's MEM_TAG_WIDTH; rename coalToVxCacheNode

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This commit is contained in:
Hansung Kim
2023-11-28 16:53:41 -08:00
parent c5e37dd3b8
commit b66be6c3ae
2 changed files with 31 additions and 18 deletions
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3
src/main/scala/tile/VortexTile.scala
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@@ -283,8 +283,7 @@ class VortexTile private (
val l1cache = LazyModule(new VortexL1Cache(vortexL1Config))
// Connect L1 with imem_fetch_interface without XBar
// coalToVxCacheNode is a bad naming, it really means up steam of vxBank in whihc it takes input
// imemNodes.foreach { l1cache.icache_bank.coalToVxCacheNode := TLWidthWidget(4) := _ }
// imemNodes.foreach { l1cache.icache_bank.coresideNode := TLWidthWidget(4) := _ }
imemNodes.foreach { l1cache.coresideNode := TLWidthWidget(4) := _ }
// dmemNodes go through coalescerNode
l1cache.coresideNode :=* coalescerNode