From b66be6c3ae7edddf133bcded9173dbe0d158c73d Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 28 Nov 2023 16:53:41 -0800 Subject: [PATCH] Respect VX_cache's MEM_TAG_WIDTH; rename coalToVxCacheNode --- src/main/scala/rocket/VortexBank.scala | 46 +++++++++++++++++--------- src/main/scala/tile/VortexTile.scala | 3 +- 2 files changed, 31 insertions(+), 18 deletions(-) diff --git a/src/main/scala/rocket/VortexBank.scala b/src/main/scala/rocket/VortexBank.scala index a0b9e3f..e642415 100644 --- a/src/main/scala/rocket/VortexBank.scala +++ b/src/main/scala/rocket/VortexBank.scala @@ -49,8 +49,8 @@ class VortexL1Cache(config: VortexL1Config)(implicit p: Parameters) // dcache banks val dcache_banks = Seq.tabulate(config.numBanks) { bankId => - val bank = LazyModule(new VortexBank(config, bankId)) - bank + val dcache_bank = LazyModule(new VortexBank(config, bankId)) + dcache_bank } // passthrough val passThrough = LazyModule(new VortexBankPassThrough(config)) @@ -61,9 +61,9 @@ class VortexL1Cache(config: VortexL1Config)(implicit p: Parameters) // core-side crossbar that arbitrates core requests to banks protected val bankXbar = LazyModule(new TLXbar) bankXbar.node :=* coresideNode - dcache_banks.foreach { _.coalToVxCacheNode :=* bankXbar.node } - passThrough.coalToVxCacheNode :=* bankXbar.node - icache_bank.coalToVxCacheNode :=* bankXbar.node + dcache_banks.foreach { _.coresideNode :=* bankXbar.node } + passThrough.coresideNode :=* bankXbar.node + icache_bank.coresideNode :=* bankXbar.node // master node that exposes to and drives the downstream val masterNode = TLIdentityNode() @@ -101,7 +101,12 @@ class VortexBankPassThrough(config: VortexL1Config)(implicit p: Parameters) clients = Seq( TLMasterParameters.v1( name = "VortexBank", - sourceId = IdRange(0, 1 << (log2Ceil(config.memSideSourceIds) + 5 /*FIXME: why is this here?*/)), + sourceId = IdRange( + 0, + 1 << (log2Ceil( + config.memSideSourceIds + ) + 5 /*FIXME: give more sourceId so that passthrough doesn't block; hacky*/ ) + ), supportsProbe = TransferSizes(1, config.wordSize), supportsGet = TransferSizes(1, config.wordSize), supportsPutFull = TransferSizes(1, config.wordSize), @@ -111,14 +116,14 @@ class VortexBankPassThrough(config: VortexL1Config)(implicit p: Parameters) ) ) - val coalToVxCacheNode = TLManagerNode(managerParam) + val coresideNode = TLManagerNode(managerParam) val vxCacheFetchNode = TLClientNode(clientParam) val vxCacheToL2Node = TLIdentityNode() vxCacheToL2Node := TLWidthWidget(config.cacheLineSize) := vxCacheFetchNode // the implementation to make everything a pass through lazy val module = new LazyModuleImp(this) { - val (upstream, _) = coalToVxCacheNode.in(0) + val (upstream, _) = coresideNode.in(0) val (downstream, _) = vxCacheFetchNode.out(0) downstream.a <> upstream.a @@ -187,7 +192,8 @@ class VortexBank( ) ) - val coalToVxCacheNode = TLManagerNode(managerParam) + // Core -> VxCache + val coresideNode = TLManagerNode(managerParam) val vxCacheToL2Node = TLIdentityNode() val vxCacheFetchNode = TLClientNode(clientParam) @@ -207,7 +213,9 @@ class VortexBankImp( WORD_SIZE = config.wordSize, CACHE_LINE_SIZE = config.cacheLineSize, CORE_TAG_WIDTH = config.coreTagPlusSizeWidth, - MSHR_SIZE = config.mshrSize + // MSHR_SIZE = config.mshrSize + // NUM_BANKS is set to 1 to treat a whole VX_cache_top instance as a + // single bank ) ); @@ -250,7 +258,7 @@ class VortexBankImp( // Translate TL request from Coalescer to requests for VX_cache def TLReq2VXReq = { - val (tlInFromCoal, _) = outer.coalToVxCacheNode.in.head + val (tlInFromCoal, _) = outer.coresideNode.in.head // coal -> vxCache tlInFromCoal.a.ready := @@ -407,8 +415,6 @@ class VX_cache_top( CORE_TAG_WIDTH: Int = 16, // source ID ranges from 0 to 1 << 10, we need to allocate upper bits to save size WORD_ADDR_WIDTH: Int = 28, // 16 byte "word" = 4 bits - MEM_TAG_WIDTH: Int = - 14, // Elaborated value is also completely different from (32 - log2Ceil(CACHE_LINE_SIZE)). This should match with sourceIds on client node associated with this cache MEM_ADDR_WIDTH: Int = 28 // 16 byte cache line = 4 bits ) extends BlackBox( Map( @@ -425,12 +431,20 @@ class VX_cache_top( "WRITE_ENABLE" -> WRITE_ENABLE, "UUID_WIDTH" -> UUID_WIDTH, "TAG_WIDTH" -> CORE_TAG_WIDTH, - "MEM_TAG_WIDTH" -> MEM_TAG_WIDTH, + // Although VX_cache_top exposes it as a parameter, MEM_TAG_WIDTH is + // not really configurable -- it is set to be a concatenation of the + // MSHR id and cache bank id. Instead of trying to configure it from + // Chisel side, we try to figure out its value that's elaborated in the + // Verilog side and configure the Chisel io width correspondingly. + // "MEM_TAG_WIDTH" -> MEM_TAG_WIDTH ) ) with HasBlackBoxResource { - // require(MEM_) + def memTagWidth(mshrSize: Int, numBanks: Int): Int = + log2Ceil(mshrSize) + log2Ceil(numBanks) + val MEM_TAG_WIDTH = memTagWidth(MSHR_SIZE, NUM_BANKS) + println(s"====== VortexBank: MEM_TAG_WIDTH = ${MEM_TAG_WIDTH}") val io = IO(new Bundle { val clk = Input(Clock()) @@ -466,7 +480,7 @@ class VX_cache_top( }) addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_bank.sv") - addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_bypass.sv") + // addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_bypass.sv") addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_data.sv") addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_define.vh") addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_init.sv") diff --git a/src/main/scala/tile/VortexTile.scala b/src/main/scala/tile/VortexTile.scala index 5eefadd..86f33c5 100644 --- a/src/main/scala/tile/VortexTile.scala +++ b/src/main/scala/tile/VortexTile.scala @@ -283,8 +283,7 @@ class VortexTile private ( val l1cache = LazyModule(new VortexL1Cache(vortexL1Config)) // Connect L1 with imem_fetch_interface without XBar - // coalToVxCacheNode is a bad naming, it really means up steam of vxBank in whihc it takes input - // imemNodes.foreach { l1cache.icache_bank.coalToVxCacheNode := TLWidthWidget(4) := _ } + // imemNodes.foreach { l1cache.icache_bank.coresideNode := TLWidthWidget(4) := _ } imemNodes.foreach { l1cache.coresideNode := TLWidthWidget(4) := _ } // dmemNodes go through coalescerNode l1cache.coresideNode :=* coalescerNode