Parameterize tensor core FP16

src/main/scala/radiance/subsystem/Configs.scala

@@ -37,6 +37,7 @@ class WithRadianceCores(
   n: Int,
   location: HierarchicalLocation,
   crossing: RocketCrossingParams,
+  tensorCoreFP16: Boolean,
   useVxCache: Boolean
 ) extends Config((site, _, up) => {
   case TilesLocated(`location`) => {
@@ -44,7 +45,7 @@ class WithRadianceCores(
     val idOffset = up(NumTiles)
     val coreIdOffset = up(NumRadianceCores)
     val vortex = RadianceTileParams(
-      core = VortexCoreParams(fpu = None),
+      core = VortexCoreParams(tensorCoreFP16 = tensorCoreFP16),
       btb = None,
       useVxCache = useVxCache,
       dcache = Some(DCacheParams(
@@ -77,14 +78,17 @@ class WithRadianceCores(
   case NumTiles => up(NumTiles) + n
   case NumRadianceCores => up(NumRadianceCores) + n
 }) {
-  def this(n: Int, location: HierarchicalLocation = InSubsystem, useVxCache: Boolean = false) = this(n, location, RocketCrossingParams(
+  // constructor override that omits `crossing`
+  def this(n: Int, location: HierarchicalLocation = InSubsystem,
+    tensorCoreFP16: Boolean = false, useVxCache: Boolean = false)
+  = this(n, location, RocketCrossingParams(
     master = HierarchicalElementMasterPortParams.locationDefault(location),
     slave = HierarchicalElementSlavePortParams.locationDefault(location),
     mmioBaseAddressPrefixWhere = location match {
       case InSubsystem => CBUS
       case InCluster(clusterId) => CCBUS(clusterId)
     }
-  ), useVxCache)
+  ), tensorCoreFP16, useVxCache)
 }
 
 object RadianceGemminiDataType extends Enumeration {
@@ -221,7 +225,7 @@ class WithFuzzerCores(
     val prev = up(TilesLocated(InSubsystem))
     val idOffset = up(NumTiles)
     val fuzzer = FuzzerTileParams(
-      core = VortexCoreParams(fpu = None),
+      core = VortexCoreParams(),
       useVxCache = useVxCache)
     List.tabulate(n)(i => FuzzerTileAttachParams(
       fuzzer.copy(tileId = i + idOffset),

src/main/scala/radiance/tile/RadianceTile.scala

@@ -97,6 +97,7 @@ case class VortexCoreParams(
   mimpid: Int = 0x20181004, // release date in BCD
   mulDiv: Option[MulDivParams] = None,
   fpu: Option[FPUParams] = None,
+  tensorCoreFP16: Boolean = false, // FP32 if true, FP16 if false
   debugROB: Boolean = false, // if enabled, uses a C++ debug ROB to generate trace-with-wdata
   haveCease: Boolean = true, // non-standard CEASE instruction
   haveSimTimeout: Boolean = true // add plusarg for simulation timeout

src/main/scala/radiance/tile/VortexCore.scala

@@ -122,6 +122,7 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
       // across multiple clusters.
       Map(
         "CORE_ID" -> tile.radianceParams.coreId,
+        "TENSOR_FP16" -> (if (tile.radianceParams.core.tensorCoreFP16) 1 else 0),
         // TODO: can we get this as a parameter?
         "BOOTROM_HANG100" -> 0x10100,
         "NUM_THREADS" -> tile.numLsuLanes
@@ -146,7 +147,6 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
   // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v")
   // addResource("/vsrc/vortex/hw/syn/modelsim/vortex_tb.v")
 
-
   addResource("/vsrc/vortex/hw/rtl/VX_gpu_pkg.sv")
 
   // addResource("/vsrc/vortex/hw/rtl/VX_cluster.sv")
@@ -333,8 +333,11 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
   // tensor core
   // this module is referenced from inside the Verilog RTL of the core
   // pipeline.
-  // addResource("/vsrc/TensorDotProductUnitFP32.sv")
-  addResource("/vsrc/TensorDotProductUnit.sv")
+  if (tile.radianceParams.core.tensorCoreFP16) {
+    addResource("/vsrc/TensorDotProductUnit.sv")
+  } else {
+    addResource("/vsrc/TensorDotProductUnitFP32.sv")
+  }
 
   // fpnew
   // compile order matters; package definitions (ex. fpnew_pkg) should be