wu-arch/radiance
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

quick coalescer connection fix

Browse Source
This commit is contained in:
Richard Yan
2023-04-23 21:31:25 -07:00
parent 7663a03a8c
commit a872856263
1 changed files with 1 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/tilelink/Coalescing.scala
View File

@@ -413,8 +413,6 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
val coalReqT = new ReqQueueEntry(sourceWidth, log2Ceil(config.MAX_SIZE), config.ADDR_WIDTH, config.MAX_SIZE) val coalReqT = new ReqQueueEntry(sourceWidth, log2Ceil(config.MAX_SIZE), config.ADDR_WIDTH, config.MAX_SIZE)
val coalescer = Module(new MultiCoalescer(reqQueues.head, coalReqT, config)) val coalescer = Module(new MultiCoalescer(reqQueues.head, coalReqT, config))
coalescer.io.window := reqQueues.map(_.io) coalescer.io.window := reqQueues.map(_.io)
// FIXME
coalescer.io.out_req.ready := true.B
// Per-lane request and response queues // Per-lane request and response queues
// //
@@ -460,6 +458,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
tlCoal.a.valid := coalescer.io.out_req.valid tlCoal.a.valid := coalescer.io.out_req.valid
tlCoal.a.bits := coalescer.io.out_req.bits.toTLA(edgeCoal) tlCoal.a.bits := coalescer.io.out_req.bits.toTLA(edgeCoal)
coalescer.io.out_req.ready := tlCoal.a.ready
tlCoal.b.ready := true.B tlCoal.b.ready := true.B
tlCoal.c.valid := false.B tlCoal.c.valid := false.B
tlCoal.d.ready := true.B tlCoal.d.ready := true.B