From a8728562633a1b5781e82f8522bd92ab8d7f0fe6 Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Sun, 23 Apr 2023 21:31:25 -0700 Subject: [PATCH] quick coalescer connection fix --- src/main/scala/tilelink/Coalescing.scala | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 1acf9b8..13edca1 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -413,8 +413,6 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends val coalReqT = new ReqQueueEntry(sourceWidth, log2Ceil(config.MAX_SIZE), config.ADDR_WIDTH, config.MAX_SIZE) val coalescer = Module(new MultiCoalescer(reqQueues.head, coalReqT, config)) coalescer.io.window := reqQueues.map(_.io) - // FIXME - coalescer.io.out_req.ready := true.B // Per-lane request and response queues // @@ -460,6 +458,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends tlCoal.a.valid := coalescer.io.out_req.valid tlCoal.a.bits := coalescer.io.out_req.bits.toTLA(edgeCoal) + coalescer.io.out_req.ready := tlCoal.a.ready tlCoal.b.ready := true.B tlCoal.c.valid := false.B tlCoal.d.ready := true.B