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Left out fix

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This commit is contained in:
Hansung Kim
2023-04-23 12:09:47 -07:00
parent a71c0aed73
commit a7baf57e49
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/tilelink/Coalescing.scala
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@@ -1243,8 +1243,9 @@ class TLRAMCoalescerLoggerTest(timeout: Int = 500000)(implicit p: Parameters)
class TLRAMCoalescer(implicit p: Parameters) extends LazyModule {
// TODO: use parameters for numLanes
val numLanes = 4
val filename = "test.trace"
val coal = LazyModule(new CoalescingUnit(defaultConfig))
val driver = LazyModule(new MemTraceDriver(defaultConfig))
val driver = LazyModule(new MemTraceDriver(defaultConfig, filename))
val rams = Seq.fill(numLanes + 1)( // +1 for coalesced edge
LazyModule(
// NOTE: beatBytes here sets the data bitwidth of the upstream TileLink