From a7baf57e499150e1eee03036ebf2e03fc3d14153 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Sun, 23 Apr 2023 12:09:47 -0700 Subject: [PATCH] Left out fix --- src/main/scala/tilelink/Coalescing.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 3014a96..53ad832 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -1243,8 +1243,9 @@ class TLRAMCoalescerLoggerTest(timeout: Int = 500000)(implicit p: Parameters) class TLRAMCoalescer(implicit p: Parameters) extends LazyModule { // TODO: use parameters for numLanes val numLanes = 4 + val filename = "test.trace" val coal = LazyModule(new CoalescingUnit(defaultConfig)) - val driver = LazyModule(new MemTraceDriver(defaultConfig)) + val driver = LazyModule(new MemTraceDriver(defaultConfig, filename)) val rams = Seq.fill(numLanes + 1)( // +1 for coalesced edge LazyModule( // NOTE: beatBytes here sets the data bitwidth of the upstream TileLink