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Don't set default filename in class initializers

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This commit is contained in:
Hansung Kim
2023-04-23 12:07:52 -07:00
parent b6115cc394
commit a71c0aed73
1 changed files with 7 additions and 5 deletions
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12
src/main/scala/tilelink/Coalescing.scala
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@@ -709,7 +709,7 @@ object TLUtils {
} }
} }
class MemTraceDriver(config: CoalescerConfig, filename: String = "vecadd.core1.thread4.trace")(implicit class MemTraceDriver(config: CoalescerConfig, filename: String)(implicit
p: Parameters p: Parameters
) extends LazyModule { ) extends LazyModule {
// Create N client nodes together // Create N client nodes together
@@ -922,7 +922,7 @@ class MemTraceLogger(
numLanes: Int, numLanes: Int,
// base filename for the generated trace files. full filename will be // base filename for the generated trace files. full filename will be
// suffixed depending on `reqEnable`/`respEnable`/`loggerName`. // suffixed depending on `reqEnable`/`respEnable`/`loggerName`.
filename: String = "vecadd.core1.thread4.trace", filename: String,
reqEnable: Boolean = true, reqEnable: Boolean = true,
respEnable: Boolean = true, respEnable: Boolean = true,
// filename suffix that is unique to this logger module. // filename suffix that is unique to this logger module.
@@ -1190,12 +1190,14 @@ object TracePrintf {
class TLRAMCoalescerLogger(implicit p: Parameters) extends LazyModule { class TLRAMCoalescerLogger(implicit p: Parameters) extends LazyModule {
// TODO: use parameters for numLanes // TODO: use parameters for numLanes
val numLanes = 4 val numLanes = 4
val driver = LazyModule(new MemTraceDriver(defaultConfig)) // val filename = "test.trace"
val filename = "vecadd.core1.thread4.trace"
val driver = LazyModule(new MemTraceDriver(defaultConfig, filename))
val coreSideLogger = LazyModule( val coreSideLogger = LazyModule(
new MemTraceLogger(numLanes, loggerName = "coreside") new MemTraceLogger(numLanes, filename, loggerName = "coreside")
) )
val coal = LazyModule(new CoalescingUnit(defaultConfig)) val coal = LazyModule(new CoalescingUnit(defaultConfig))
val memSideLogger = LazyModule(new MemTraceLogger(numLanes + 1, loggerName = "memside")) val memSideLogger = LazyModule(new MemTraceLogger(numLanes + 1, filename, loggerName = "memside"))
val rams = Seq.fill(numLanes + 1)( // +1 for coalesced edge val rams = Seq.fill(numLanes + 1)( // +1 for coalesced edge
LazyModule( LazyModule(
// NOTE: beatBytes here sets the data bitwidth of the upstream TileLink // NOTE: beatBytes here sets the data bitwidth of the upstream TileLink