make unified memory node modular
This commit is contained in:
Richard Yan
164
src/main/scala/radiance/memory/RWSplitterNode.scala
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164
src/main/scala/radiance/memory/RWSplitterNode.scala
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@@ -0,0 +1,164 @@
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package radiance.memory
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import chisel3._
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import chisel3.experimental.SourceInfo
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import chisel3.util._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util.BundleField
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import org.chipsalliance.cde.config.Parameters
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class RWSplitterNode(name: String = "rw_splitter")(implicit p: Parameters) extends LazyModule {
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// this node accepts both read and write requests,
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// splits & arbitrates them into one client node per type of operation;
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// there will be N incoming edges, two outgoing edges, with two N:1 muxes;
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// it keeps the read and write channels fully separate to allow parallel processing.
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val node = TLNexusNode(
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clientFn = { seq =>
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val in_mapping = TLXbar.mapInputIds(seq)
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val read_src_range = IdRange(in_mapping.map(_.start).min, in_mapping.map(_.end).max)
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assert((read_src_range.start == 0) && isPow2(read_src_range.end))
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val write_src_range = read_src_range.shift(read_src_range.size)
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val visibilities = seq.flatMap(_.masters.flatMap(_.visibility))
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val vis_min = visibilities.map(_.base).min
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val vis_max = visibilities.map{ x => x.base + x.mask }.max
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val vis_mask = vis_max - vis_min
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require(isPow2(vis_mask + 1) || vis_mask == -1)
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println(f"combined visibilities of splitter memory node clients: ${vis_min}, ${vis_mask}")
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seq(0).v1copy(
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echoFields = BundleField.union(seq.flatMap(_.echoFields)),
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requestFields = BundleField.union(seq.flatMap(_.requestFields)),
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responseKeys = seq.flatMap(_.responseKeys).distinct,
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minLatency = seq.map(_.minLatency).min,
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clients = Seq(
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TLMasterParameters.v1(
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name = s"${name}_read_client",
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sourceId = read_src_range,
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visibility = Seq(AddressSet(vis_min, vis_mask)),
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supportsProbe = TransferSizes.mincover(seq.map(_.anyEmitClaims.get)),
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supportsGet = TransferSizes.mincover(seq.map(_.anyEmitClaims.get)),
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supportsPutFull = TransferSizes.none,
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supportsPutPartial = TransferSizes.none
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),
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TLMasterParameters.v1(
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name = s"${name}_write_client",
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sourceId = write_src_range,
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visibility = Seq(AddressSet(vis_min, vis_mask)),
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supportsProbe = TransferSizes.mincover(
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seq.map(_.anyEmitClaims.putFull) ++seq.map(_.anyEmitClaims.putPartial)),
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supportsGet = TransferSizes.none,
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supportsPutFull = TransferSizes.mincover(seq.map(_.anyEmitClaims.putFull)),
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supportsPutPartial = TransferSizes.mincover(seq.map(_.anyEmitClaims.putPartial))
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)
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)
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)
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},
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managerFn = { seq =>
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println(seq.flatMap(_.slaves.map(_.supports)))
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// val fifoIdFactory = TLXbar.relabeler()
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seq(0).v1copy(
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responseFields = BundleField.union(seq.flatMap(_.responseFields)),
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requestKeys = seq.flatMap(_.requestKeys).distinct,
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minLatency = seq.map(_.minLatency).min,
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endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
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managers = Seq(TLSlaveParameters.v2(
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name = Some(s"${name}_manager"),
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address = AddressSet.unify(seq.flatMap(_.slaves.flatMap(_.address))),
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supports = TLMasterToSlaveTransferSizes(
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get = TransferSizes.mincover(seq.flatMap(_.slaves.map(_.supportsGet))),
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putFull = TransferSizes.mincover(seq.flatMap(_.slaves.map(_.supportsPutFull))),
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putPartial = TransferSizes.mincover(seq.flatMap(_.slaves.map(_.supportsPutPartial)))
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),
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fifoId = Some(0),
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))
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)
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}
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)
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lazy val module = new LazyModuleImp(this) {
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val u_out = node.out
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val u_in = node.in
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assert(u_out.length == 2)
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println(f"gemmini unified memory node has ${u_in.length} incoming client(s)")
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val r_out = u_out.head
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val w_out = u_out.last
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val in_src = TLXbar.mapInputIds(u_in.map(_._2.client))
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val in_src_size = in_src.map(_.end).max
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assert(isPow2(in_src_size)) // should be checked already, but just to be sure
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// arbitrate all reads into one read while assigning source prefix, same for write
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val a_arbiter_in = (u_in zip in_src).map { case ((in_node, _), src_range) =>
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val in_r: DecoupledIO[TLBundleA] =
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WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(in_node.a.bits.params.copy(
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sourceBits = log2Up(in_src_size) + 1
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)))))
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val in_w: DecoupledIO[TLBundleA] = WireDefault(0.U.asTypeOf(in_r.cloneType))
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val req_is_read = in_node.a.bits.opcode === TLMessages.Get
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(Seq(in_r.bits.user, in_r.bits.address, in_r.bits.opcode, in_r.bits.size,
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in_r.bits.mask, in_r.bits.param, in_r.bits.data)
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zip Seq(in_node.a.bits.user, in_node.a.bits.address, in_node.a.bits.opcode, in_node.a.bits.size,
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in_node.a.bits.mask, in_node.a.bits.param, in_node.a.bits.data))
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.foreach { case (x, y) => x := y }
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in_r.bits.source := in_node.a.bits.source | src_range.start.U | Mux(req_is_read, 0.U, in_src_size.U)
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in_w.bits := in_r.bits
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in_r.valid := in_node.a.valid && req_is_read
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in_w.valid := in_node.a.valid && !req_is_read
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in_node.a.ready := Mux(req_is_read, in_r.ready, in_w.ready)
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(in_r, in_w)
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}
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// we cannot use round robin because it might reorder requests, even from the same client
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val (a_arbiter_in_r_nodes, a_arbiter_in_w_nodes) = a_arbiter_in.unzip
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TLArbiter.lowest(r_out._2, r_out._1.a, a_arbiter_in_r_nodes:_*)
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TLArbiter.lowest(w_out._2, w_out._1.a, a_arbiter_in_w_nodes:_*)
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def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // from Xbar
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// for each unified mem node client, arbitrate read/write responses on d channel
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(u_in zip in_src).zipWithIndex.foreach { case (((in_node, in_edge), src_range), i) =>
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// assign d channel back based on source, invalid if source prefix mismatch
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val resp = Seq(r_out._1.d, w_out._1.d)
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val source_match = resp.zipWithIndex.map { case (r, i) =>
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(r.bits.source(r.bits.source.getWidth - 1) === i.U(1.W)) && // MSB indicates read(0)/write(1)
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src_range.contains(trim(r.bits.source, in_src_size))
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}
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val d_arbiter_in = resp.map(r => WireDefault(
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0.U.asTypeOf(Decoupled(new TLBundleD(r.bits.params.copy(
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sourceBits = in_node.d.bits.source.getWidth,
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sizeBits = in_node.d.bits.size.getWidth
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))))
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))
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(d_arbiter_in lazyZip resp lazyZip source_match).foreach { case (arb_in: DecoupledIO[TLBundleD], r, sm) =>
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(Seq(arb_in.bits.user, arb_in.bits.opcode, arb_in.bits.data, arb_in.bits.param,
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arb_in.bits.sink, arb_in.bits.denied, arb_in.bits.corrupt)
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zip Seq(r.bits.user, r.bits.opcode, r.bits.data, r.bits.param,
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r.bits.sink, r.bits.denied, r.bits.corrupt))
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.foreach { case (x, y) => x := y }
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arb_in.bits.source := trim(r.bits.source, 1 << in_node.d.bits.source.getWidth) // we can trim b/c isPow2(prefix)
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arb_in.bits.size := trim(r.bits.size, 1 << in_node.d.bits.size.getWidth) // FIXME: check truncation
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arb_in.valid := r.valid && sm
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r.ready := arb_in.ready
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}
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TLArbiter.robin(in_edge, in_node.d, d_arbiter_in:_*)
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}
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}
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}
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object RWSplitterNode {
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def apply()(implicit p: Parameters, valName: ValName, sourceInfo: SourceInfo): TLNexusNode = {
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LazyModule(new RWSplitterNode(name = valName.name)).node
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}
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def apply(name: String)(implicit p: Parameters, valName: ValName, sourceInfo: SourceInfo): TLNexusNode = {
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LazyModule(new RWSplitterNode(name = name)).node
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}
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}
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@@ -13,6 +13,7 @@ import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util.BundleField
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import gemmini._
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import org.chipsalliance.cde.config.Parameters
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import radiance.memory.RWSplitterNode
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case class RadianceClusterParams(
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val clusterId: Int,
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@@ -77,78 +78,24 @@ class RadianceCluster (
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val smem_banks = gemminiConfig.sp_banks
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val smem_subbanks = 1
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val splitter_node = RWSplitterNode()
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unified_mem_read_node :=* TLWidthWidget(spad_data_len) :=* gemmini.spad_read_nodes
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// unified_mem_read_node :=* TLWidthWidget(acc_data_len) :=* acc_read_nodes
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unified_mem_write_node :=* TLWidthWidget(spad_data_len) :=* gemmini.spad_write_nodes
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// unified_mem_write_node :=* TLWidthWidget(acc_data_len) :=* acc_write_nodes
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unified_mem_write_node := gemmini.spad.spad_writer.node // this is the dma write node
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// unified_mem_read_node :=* TLWidthWidget(acc_data_len) :=* acc_read_nodes
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// unified_mem_write_node :=* TLWidthWidget(acc_data_len) :=* acc_write_nodes
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// this node accepts both read and write requests,
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// splits & arbitrates them into one client node per type of operation
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// it keeps the read and write channels fully separate to allow parallel processing
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val unified_mem_node = TLNexusNode(
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clientFn = { seq =>
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val in_mapping = TLXbar.mapInputIds(seq)
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val read_src_range = IdRange(in_mapping.map(_.start).min, in_mapping.map(_.end).max)
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assert((read_src_range.start == 0) && isPow2(read_src_range.end))
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val write_src_range = read_src_range.shift(read_src_range.size)
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val visibilities = seq.flatMap(_.masters.flatMap(_.visibility))
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val vis_min = visibilities.map(_.base).min
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val vis_max = visibilities.map{ x => x.base + x.mask }.max
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val vis_mask = vis_max - vis_min
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require(isPow2(vis_mask + 1) || vis_mask == -1)
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println(f"combined visibilities of unified memory node clients: ${vis_min}, ${vis_mask}")
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// assert(splitter_node.in.map(_._2.slave.slaves.flatMap(_.supports.get)))
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seq(0).v1copy(
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echoFields = BundleField.union(seq.flatMap(_.echoFields)),
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requestFields = BundleField.union(seq.flatMap(_.requestFields)),
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responseKeys = seq.flatMap(_.responseKeys).distinct,
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minLatency = seq.map(_.minLatency).min,
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clients = Seq(
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TLMasterParameters.v1(
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name = "unified_mem_read_client",
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sourceId = read_src_range,
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visibility = Seq(AddressSet(vis_min, vis_mask)),
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supportsProbe = TransferSizes.mincover(seq.map(_.anyEmitClaims.get)),
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supportsGet = TransferSizes.mincover(seq.map(_.anyEmitClaims.get)),
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supportsPutFull = TransferSizes.none,
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supportsPutPartial = TransferSizes.none
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),
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TLMasterParameters.v1(
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name = "unified_mem_write_client",
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sourceId = write_src_range,
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visibility = Seq(AddressSet(vis_min, vis_mask)),
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supportsProbe = TransferSizes.mincover(
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seq.map(_.anyEmitClaims.putFull) ++seq.map(_.anyEmitClaims.putPartial)),
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supportsGet = TransferSizes.none,
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supportsPutFull = TransferSizes.mincover(seq.map(_.anyEmitClaims.putFull)),
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supportsPutPartial = TransferSizes.mincover(seq.map(_.anyEmitClaims.putPartial))
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)
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)
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)
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},
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managerFn = { seq =>
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// val fifoIdFactory = TLXbar.relabeler()
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seq(0).v1copy(
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responseFields = BundleField.union(seq.flatMap(_.responseFields)),
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requestKeys = seq.flatMap(_.requestKeys).distinct,
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minLatency = seq.map(_.minLatency).min,
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endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
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managers = Seq(TLSlaveParameters.v2(
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name = Some(f"unified_mem_manager"),
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address = Seq(AddressSet(gemmini.spad_base, smem_depth * smem_width * smem_banks - 1)),
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supports = TLMasterToSlaveTransferSizes(
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get = TransferSizes(1, smem_width),
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putFull = TransferSizes(1, smem_width),
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putPartial = TransferSizes(1, smem_width)),
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fifoId = Some(0)
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))
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)
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}
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)
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/* address = Seq(AddressSet(gemmini.spad_base, smem_depth * smem_width * smem_banks - 1)),
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supports = TLMasterToSlaveTransferSizes(
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get = TransferSizes(1, smem_width),
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putFull = TransferSizes(1, smem_width),
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putPartial = TransferSizes(1, smem_width)),*/
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unified_mem_read_node := TLWidthWidget(spad_data_len) := unified_mem_node
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unified_mem_write_node := TLWidthWidget(spad_data_len) := unified_mem_node
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unified_mem_read_node := TLWidthWidget(spad_data_len) := splitter_node
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unified_mem_write_node := TLWidthWidget(spad_data_len) := splitter_node
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val stride_by_word = false
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// collection of read and write managers for each sram (sub)bank
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@@ -206,7 +153,7 @@ class RadianceCluster (
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// connect tile smem nodes to xbar, and xbar to banks
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// val smem_xbar = TLXbar()
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unified_mem_node :=* TLWidthWidget(4) :=* clbus.outwardNode
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splitter_node :=* TLWidthWidget(4) :=* clbus.outwardNode
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gemminiTile.slaveNode :=* TLWidthWidget(4) :=* clbus.outwardNode
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// printf and perf counter buffer FIXME: make configurable
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TLRAM(AddressSet(x"ff004000", numCores * 0x200 - 1)) := TLFragmenter(4, 4) := clbus.outwardNode
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@@ -345,83 +292,7 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp(
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}
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}
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def connectUnifiedMemNode: Unit = {
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val u_out = outer.unified_mem_node.out
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val u_in = outer.unified_mem_node.in
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assert(u_out.length == 2)
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println(f"gemmini unified memory node has ${u_in.length} incoming client(s)")
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val r_out = u_out.head
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val w_out = u_out.last
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val in_src = TLXbar.mapInputIds(u_in.map(_._2.client))
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val in_src_size = in_src.map(_.end).max
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assert(isPow2(in_src_size)) // should be checked already, but just to be sure
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// arbitrate all reads into one read while assigning source prefix, same for write
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val a_arbiter_in = (u_in zip in_src).map { case ((in_node, _), src_range) =>
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val in_r: DecoupledIO[TLBundleA] =
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WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(in_node.a.bits.params.copy(
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sourceBits = log2Up(in_src_size) + 1
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)))))
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val in_w: DecoupledIO[TLBundleA] = WireDefault(0.U.asTypeOf(in_r.cloneType))
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val req_is_read = in_node.a.bits.opcode === TLMessages.Get
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(Seq(in_r.bits.user, in_r.bits.address, in_r.bits.opcode, in_r.bits.size,
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in_r.bits.mask, in_r.bits.param, in_r.bits.data)
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zip Seq(in_node.a.bits.user, in_node.a.bits.address, in_node.a.bits.opcode, in_node.a.bits.size,
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in_node.a.bits.mask, in_node.a.bits.param, in_node.a.bits.data))
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.foreach { case (x, y) => x := y }
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in_r.bits.source := in_node.a.bits.source | src_range.start.U | Mux(req_is_read, 0.U, in_src_size.U)
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in_w.bits := in_r.bits
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in_r.valid := in_node.a.valid && req_is_read
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in_w.valid := in_node.a.valid && !req_is_read
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in_node.a.ready := Mux(req_is_read, in_r.ready, in_w.ready)
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(in_r, in_w)
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}
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// we cannot use round robin because it might reorder requests, even from the same client
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val (a_arbiter_in_r_nodes, a_arbiter_in_w_nodes) = a_arbiter_in.unzip
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TLArbiter.lowest(r_out._2, r_out._1.a, a_arbiter_in_r_nodes:_*)
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TLArbiter.lowest(w_out._2, w_out._1.a, a_arbiter_in_w_nodes:_*)
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def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // from Xbar
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// for each unified mem node client, arbitrate read/write responses on d channel
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(u_in zip in_src).zipWithIndex.foreach { case (((in_node, in_edge), src_range), i) =>
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// assign d channel back based on source, invalid if source prefix mismatch
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val resp = Seq(r_out._1.d, w_out._1.d)
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val source_match = resp.zipWithIndex.map { case (r, i) =>
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(r.bits.source(r.bits.source.getWidth - 1) === i.U(1.W)) && // MSB indicates read(0)/write(1)
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src_range.contains(trim(r.bits.source, in_src_size))
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}
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val d_arbiter_in = resp.map(r => WireDefault(
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0.U.asTypeOf(Decoupled(new TLBundleD(r.bits.params.copy(
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sourceBits = in_node.d.bits.source.getWidth,
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sizeBits = in_node.d.bits.size.getWidth
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))))
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))
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(d_arbiter_in lazyZip resp lazyZip source_match).foreach { case (arb_in, r, sm) =>
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(Seq(arb_in.bits.user, arb_in.bits.opcode, arb_in.bits.data, arb_in.bits.param,
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arb_in.bits.sink, arb_in.bits.denied, arb_in.bits.corrupt)
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zip Seq(r.bits.user, r.bits.opcode, r.bits.data, r.bits.param,
|
||||
r.bits.sink, r.bits.denied, r.bits.corrupt))
|
||||
.foreach { case (x, y) => x := y }
|
||||
arb_in.bits.source := trim(r.bits.source, 1 << in_node.d.bits.source.getWidth) // we can trim b/c isPow2(prefix)
|
||||
arb_in.bits.size := trim(r.bits.size, 1 << in_node.d.bits.size.getWidth) // FIXME: check truncation
|
||||
|
||||
arb_in.valid := r.valid && sm
|
||||
r.ready := arb_in.ready
|
||||
}
|
||||
|
||||
TLArbiter.robin(in_edge, in_node.d, d_arbiter_in:_*)
|
||||
}
|
||||
}
|
||||
|
||||
makeSmemBanks
|
||||
connectUnifiedMemNode
|
||||
|
||||
println(s"======== barrierSlaveNode: ${outer.barrierSlaveNode.in(0)._2.barrierIdBits}")
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user