From 9d8e9de8d0afdc5bccfa3dd660795115fe9b2041 Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Thu, 19 Oct 2023 16:14:35 -0700 Subject: [PATCH] differentiate addresses for different harts --- src/main/scala/tile/VortexTile.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/tile/VortexTile.scala b/src/main/scala/tile/VortexTile.scala index 1a34a3f..7e0d570 100644 --- a/src/main/scala/tile/VortexTile.scala +++ b/src/main/scala/tile/VortexTile.scala @@ -61,9 +61,9 @@ class VortexTile private( val slaveNode = TLIdentityNode() val masterNode = visibilityNode - val regDevice = new SimpleDevice("vortex-reg", Seq("vortex-reg")) + val regDevice = new SimpleDevice("vortex-reg", Seq(s"vortex-reg${tileParams.hartId}")) val regNode = TLRegisterNode( - address = Seq(AddressSet(0x7c000000, 0xfff)), + address = Seq(AddressSet(0x7c000000 + 0x1000 * tileParams.hartId, 0xfff)), device = regDevice, beatBytes = 4, concurrency = 1) @@ -156,7 +156,7 @@ class VortexTile private( val beuProperty = bus_error_unit.map(d => Map( "sifive,buserror" -> d.device.asProperty)).getOrElse(Nil) - val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,vortex0", "riscv")) { + val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq(s"sifive,vortex${tileParams.hartId}", "riscv")) { override def parent = Some(ResourceAnchors.cpus) override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources)