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Instantiate multiple TLRAMs as sharedmem banks

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Hansung Kim
2024-01-01 12:49:23 -08:00
parent 95e05f5457
commit 8c12c7af16
2 changed files with 27 additions and 16 deletions
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2
src/main/scala/rocket/VortexCache.scala
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@@ -139,8 +139,8 @@ class VortexBank(
// suppose have 4 bank // suppose have 4 bank
// base for bank 1: ...000000|01|0000 // base for bank 1: ...000000|01|0000
// mask for bank 1; 111111|00|1111 // mask for bank 1; 111111|00|1111
val mask = 0xffffffffL ^ ((config.numBanks - 1) * config.wordSize)
val base = 0x00000000L | (bankId * config.wordSize) val base = 0x00000000L | (bankId * config.wordSize)
val mask = 0xffffffffL ^ ((config.numBanks - 1) * config.wordSize)
val excludeSets = config.uncachedAddrSets val excludeSets = config.uncachedAddrSets
var remainingSets: Seq[AddressSet] = Seq(AddressSet(base, mask)) var remainingSets: Seq[AddressSet] = Seq(AddressSet(base, mask))

41
src/main/scala/tile/VortexTile.scala
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@@ -323,13 +323,22 @@ class VortexTile private (
} }
} }
// Instantiate sharedmem // Instantiate sharedmem banks
//
// Instantiate the same number of banks as there are lanes.
// TODO: parametrize // TODO: parametrize
// FIXME: beatBytes should be wordSize val smemBanks = Seq.tabulate(numLanes) { bankId =>
val sharedmem = LazyModule(new TLRAM(AddressSet(0xff000000L, 0x00ffffffL), beatBytes = 4)) // Banked-by-word (4 bytes)
// base for bank 1: ff...000000|01|00
// mask for bank 1; 00...111111|00|11
val base = 0xff000000L | (bankId * 4 /*wordSize*/ )
val mask = 0x00ffffffL ^ ((numLanes - 1) * 4 /*wordSize*/ )
LazyModule(new TLRAM(AddressSet(base, mask), beatBytes = 4 /*wordSize*/ ))
}
// smem lanes-to-banks crossbar
val smemXbar = LazyModule(new TLXbar) val smemXbar = LazyModule(new TLXbar)
smemNodes.foreach(smemXbar.node := _) smemNodes.foreach(smemXbar.node := _)
sharedmem.node :=* smemXbar.node smemBanks.foreach(_.node := smemXbar.node)
if (vortexParams.useVxCache) { if (vortexParams.useVxCache) {
tlMasterXbar.node := TLWidthWidget(16) := memNode tlMasterXbar.node := TLWidthWidget(16) := memNode
@@ -557,18 +566,19 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
val matchingSources = Wire(UInt(outer.numLanes.W)) val matchingSources = Wire(UInt(outer.numLanes.W))
matchingSources := dmemBundles matchingSources := dmemBundles
.map(b => .map(b =>
// If there is no valid response pending across all lanes, // If there is no valid response pending across all lanes,
// matchingSources should not filter out upstream ready signals, so // matchingSources should not filter out upstream ready signals, so
// set it to all-1 // set it to all-1
!arb.io.out.valid || (b.bits.source === arb.io.out.bits) !arb.io.out.valid || (b.bits.source === arb.io.out.bits)
) )
.asUInt .asUInt
// make connection: // make connection:
// VortexBundle <--> sourceId filter <--> VortexTLAdapter <--> dmemNodes // VortexBundle <--> sourceId filter <--> VortexTLAdapter <--> dmemNodes
(core.io.dmem.get zip dmemTLAdapters) foreach { case (coreMem, tlAdapter) => (core.io.dmem.get zip dmemTLAdapters) foreach {
tlAdapter.io.inReq <> coreMem.a case (coreMem, tlAdapter) =>
coreMem.d <> tlAdapter.io.inResp tlAdapter.io.inReq <> coreMem.a
coreMem.d <> tlAdapter.io.inResp
} }
// override response channel with matchingSources // override response channel with matchingSources
(core.io.dmem.get zip dmemTLAdapters).zipWithIndex.foreach { (core.io.dmem.get zip dmemTLAdapters).zipWithIndex.foreach {
@@ -601,9 +611,10 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
) )
) )
} }
(core.io.smem.get zip smemTLAdapters) foreach { case (coreMem, tlAdapter) => (core.io.smem.get zip smemTLAdapters) foreach {
tlAdapter.io.inReq <> coreMem.a case (coreMem, tlAdapter) =>
coreMem.d <> tlAdapter.io.inResp tlAdapter.io.inReq <> coreMem.a
coreMem.d <> tlAdapter.io.inResp
} }
(smemTLAdapters zip smemTLBundles) foreach { case (tlAdapter, tlOut) => (smemTLAdapters zip smemTLBundles) foreach { case (tlAdapter, tlOut) =>
tlOut.a <> tlAdapter.io.outReq tlOut.a <> tlAdapter.io.outReq