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tensor: Fix tagWidth for tensor mem io

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This commit is contained in:
Hansung Kim
2024-10-22 16:26:08 -07:00
parent c613341a77
commit 8818fc9203
1 changed files with 10 additions and 6 deletions
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16
src/main/scala/radiance/tile/RadianceTile.scala
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@@ -739,7 +739,7 @@ class RadianceTileModuleImp(outer: RadianceTile)
}
}
def connectTc {
def connectTensor = {
val tcb0 = new {
val addr = core.io.tc_a_bits_address(31, 0)
val tag = core.io.tc_a_bits_tag(3, 0)
@@ -758,16 +758,18 @@ class RadianceTileModuleImp(outer: RadianceTile)
val adapter = Module(
new VortexTLAdapter(
outer.smemSourceWidth,
new VortexBundleA(tagWidth = 1, dataWidth = 32 * 8),
new VortexBundleD(tagWidth = 1, dataWidth = 32 * 8),
new VortexBundleA(tagWidth = 4, dataWidth = 32 * 8),
new VortexBundleD(tagWidth = 4, dataWidth = 32 * 8),
client
)
)
require(adapter.io.inReq.bits.source.widthOption.get == bundle.tag.widthOption.get)
require(adapter.io.inReq.bits.address.widthOption.get == bundle.addr.widthOption.get)
adapter.io.inReq.bits <> DontCare
adapter.io.inReq.valid := bundle.aValid
adapter.io.inReq.bits.address := bundle.addr
adapter.io.inReq.bits.source := bundle.tag
adapter.io.inReq.bits.size := 5.U
adapter.io.inReq.bits.size := 5.U // 256 bits
adapter.io.inReq.bits.opcode := TLMessages.Get
adapter.io.inReq.bits.mask := x"ffffffff".U
adapter.io.inResp.ready := bundle.dReady
@@ -780,6 +782,8 @@ class RadianceTileModuleImp(outer: RadianceTile)
core.io.tc_d_valid := Cat(adapters.last.io.inResp.valid, adapters.head.io.inResp.valid)
core.io.tc_d_bits_data := Cat(adapters.last.io.inResp.bits.data, adapters.head.io.inResp.bits.data)
core.io.tc_d_bits_tag := Cat(adapters.last.io.inResp.bits.source, adapters.head.io.inResp.bits.source)
require(core.io.tc_d_bits_data.widthOption.get == adapters.head.io.inResp.bits.data.widthOption.get * 2)
require(core.io.tc_d_bits_tag.widthOption.get == adapters.head.io.inResp.bits.source.widthOption.get * 2)
}
def connectBarrier = {
@@ -796,7 +800,7 @@ class RadianceTileModuleImp(outer: RadianceTile)
outer.barrierMasterNode.out(0)._1.resp.ready := true.B
}
def connectAccelerator: Unit = {
def connectAccelerator = {
outer.accMasterNode.out.head._1.cmd.bits := core.io.acc_write_out
outer.accMasterNode.out.head._1.cmd.valid := core.io.acc_write_en
core.io.acc_read_in := outer.accMasterNode.out.head._1.status
@@ -837,7 +841,7 @@ class RadianceTileModuleImp(outer: RadianceTile)
connectImem
connectDmem
connectSmem
connectTc
connectTensor
connectBarrier
connectAccelerator
}