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bug fixes for address rewriter

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This commit is contained in:
Richard Yan
2024-02-07 14:45:55 -08:00
parent 9451f513bf
commit 7f78f6bd2f
2 changed files with 16 additions and 12 deletions
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16
src/main/scala/radiance/memory/AddressRewriterNode.scala
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@@ -8,21 +8,25 @@ import freechips.rocketchip.tilelink.TLAdapterNode
import org.chipsalliance.cde.config.Parameters import org.chipsalliance.cde.config.Parameters
class AddressRewriterNode(baseAddr: BigInt)(implicit p: Parameters) extends LazyModule { class AddressRewriterNode(rewriteFn: UInt => UInt)(implicit p: Parameters) extends LazyModule {
require(isPow2(baseAddr) || (baseAddr == 0), "base address must be a power of 2")
val node = TLAdapterNode(clientFn = c => c, managerFn = m => m) val node = TLAdapterNode(clientFn = c => c, managerFn = m => m)
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
(node.in.map(_._1) zip node.out.map(_._1)).foreach { case (i, o) => (node.in.map(_._1) zip node.out.map(_._1)).foreach { case (i, o) =>
o.a <> i.a o.a <> i.a
o.a.bits.address := i.a.bits.address | baseAddr.U o.a.bits.address := rewriteFn(i.a.bits.address)
i.d <> o.d i.d <> o.d
} }
} }
} }
object AddressRewriterNode { object AddressOrNode {
def apply(baseAddr: BigInt)(implicit p: Parameters, valName: ValName, sourceInfo: SourceInfo): TLAdapterNode = { def apply(baseAddr: BigInt)(implicit p: Parameters, valName: ValName, sourceInfo: SourceInfo): TLAdapterNode = {
LazyModule(new AddressRewriterNode(baseAddr)).node LazyModule(new AddressRewriterNode(x => x | baseAddr.U)).node
}
}
object AddressAndNode {
def apply(baseAddr: BigInt)(implicit p: Parameters, valName: ValName, sourceInfo: SourceInfo): TLAdapterNode = {
LazyModule(new AddressRewriterNode(x => x & baseAddr.U)).node
} }
} }

10
src/main/scala/radiance/tile/RadianceTile.scala
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@@ -339,11 +339,11 @@ class RadianceTile private (
} }
if (radianceParams.useVxCache) { if (radianceParams.useVxCache) {
tlMasterXbar.node := AddressRewriterNode(base) := TLWidthWidget(16) := memNode tlMasterXbar.node := AddressOrNode(base) := TLWidthWidget(16) := memNode
} else { } else {
// imemNodes.foreach { tlMasterXbar.node := TLWidthWidget(4) := _ } // imemNodes.foreach { tlMasterXbar.node := TLWidthWidget(4) := _ }
tlMasterXbar.node :=* AddressRewriterNode(base) :=* icacheNode tlMasterXbar.node :=* AddressOrNode(base) :=* icacheNode
tlMasterXbar.node :=* AddressRewriterNode(base) :=* dcacheNode tlMasterXbar.node :=* AddressOrNode(base) :=* dcacheNode
} }
@@ -351,8 +351,8 @@ class RadianceTile private (
// TODO: parametrize // TODO: parametrize
val gemmini = LazyModule(new Gemmini(GemminiCustomConfigs.unifiedMemConfig)) val gemmini = LazyModule(new Gemmini(GemminiCustomConfigs.unifiedMemConfig))
val roccs: Seq[LazyRoCC] = Seq(gemmini) val roccs: Seq[LazyRoCC] = Seq(gemmini)
tlMasterXbar.node :=* AddressRewriterNode(base) :=* gemmini.atlNode tlMasterXbar.node :=* AddressOrNode(base) :=* gemmini.atlNode
tlOtherMastersNode :=* AddressRewriterNode(base) :=* gemmini.tlNode tlOtherMastersNode :=* AddressOrNode(base) :=* gemmini.tlNode
// MMIO // MMIO
gemmini.stlNode :=* TLWidthWidget(4) :=* smemXbar.node gemmini.stlNode :=* TLWidthWidget(4) :=* smemXbar.node