diff --git a/src/main/scala/radiance/memory/AddressRewriterNode.scala b/src/main/scala/radiance/memory/AddressRewriterNode.scala
index c0bae8c..248fff4 100644
--- a/src/main/scala/radiance/memory/AddressRewriterNode.scala
+++ b/src/main/scala/radiance/memory/AddressRewriterNode.scala
@@ -8,21 +8,25 @@ import freechips.rocketchip.tilelink.TLAdapterNode
 import org.chipsalliance.cde.config.Parameters
 
 
-class AddressRewriterNode(baseAddr: BigInt)(implicit p: Parameters) extends LazyModule {
-  require(isPow2(baseAddr) || (baseAddr == 0), "base address must be a power of 2")
-
+class AddressRewriterNode(rewriteFn: UInt => UInt)(implicit p: Parameters) extends LazyModule {
   val node = TLAdapterNode(clientFn = c => c, managerFn = m => m)
   lazy val module = new LazyModuleImp(this) {
     (node.in.map(_._1) zip node.out.map(_._1)).foreach { case (i, o) =>
       o.a <> i.a
-      o.a.bits.address := i.a.bits.address | baseAddr.U
+      o.a.bits.address := rewriteFn(i.a.bits.address)
       i.d <> o.d
     }
   }
 }
 
-object AddressRewriterNode {
+object AddressOrNode {
   def apply(baseAddr: BigInt)(implicit p: Parameters, valName: ValName, sourceInfo: SourceInfo): TLAdapterNode = {
-    LazyModule(new AddressRewriterNode(baseAddr)).node
+    LazyModule(new AddressRewriterNode(x => x | baseAddr.U)).node
   }
-}
\ No newline at end of file
+}
+
+object AddressAndNode {
+  def apply(baseAddr: BigInt)(implicit p: Parameters, valName: ValName, sourceInfo: SourceInfo): TLAdapterNode = {
+    LazyModule(new AddressRewriterNode(x => x & baseAddr.U)).node
+  }
+}
diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala
index 15c16b6..98f03d0 100644
--- a/src/main/scala/radiance/tile/RadianceTile.scala
+++ b/src/main/scala/radiance/tile/RadianceTile.scala
@@ -339,11 +339,11 @@ class RadianceTile private (
   }
 
   if (radianceParams.useVxCache) {
-    tlMasterXbar.node := AddressRewriterNode(base) := TLWidthWidget(16) := memNode
+    tlMasterXbar.node := AddressOrNode(base) := TLWidthWidget(16) := memNode
   } else {
     // imemNodes.foreach { tlMasterXbar.node := TLWidthWidget(4) := _ }
-    tlMasterXbar.node :=* AddressRewriterNode(base) :=* icacheNode
-    tlMasterXbar.node :=* AddressRewriterNode(base) :=* dcacheNode
+    tlMasterXbar.node :=* AddressOrNode(base) :=* icacheNode
+    tlMasterXbar.node :=* AddressOrNode(base) :=* dcacheNode
   }
 
 
@@ -351,8 +351,8 @@ class RadianceTile private (
   // TODO: parametrize
   val gemmini = LazyModule(new Gemmini(GemminiCustomConfigs.unifiedMemConfig))
   val roccs: Seq[LazyRoCC] = Seq(gemmini)
-  tlMasterXbar.node :=* AddressRewriterNode(base) :=* gemmini.atlNode
-  tlOtherMastersNode :=* AddressRewriterNode(base) :=* gemmini.tlNode
+  tlMasterXbar.node :=* AddressOrNode(base) :=* gemmini.atlNode
+  tlOtherMastersNode :=* AddressOrNode(base) :=* gemmini.tlNode
 
   // MMIO
   gemmini.stlNode :=* TLWidthWidget(4) :=* smemXbar.node