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Add safety assert on sourceWidth

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See commit 0d92eb65.
This commit is contained in:
Hansung Kim
2023-10-25 18:17:03 -07:00
parent 09f512fda7
commit 78e193db42
1 changed files with 4 additions and 0 deletions
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4
src/main/scala/tile/VortexTile.scala
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@@ -160,6 +160,10 @@ class VortexTile private (
case Some(simtParam) => log2Ceil(simtParam.nSrcIds) case Some(simtParam) => log2Ceil(simtParam.nSrcIds)
case None => 4 case None => 4
} }
require(sourceWidth >= 4,
"Allocating a small number of sourceIds may cause correctness bug inside " +
"Vortex core due to unconstrained synchronization issues between warps." +
"We recommend setting nSrcIds to at least 16.")
val imemNodes = Seq.tabulate(1) { i => val imemNodes = Seq.tabulate(1) { i =>
TLClientNode(Seq(TLMasterPortParameters.v1( TLClientNode(Seq(TLMasterPortParameters.v1(