From 78e193db42f50be05f50c86e2faec57613a827eb Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Wed, 25 Oct 2023 18:17:03 -0700
Subject: [PATCH] Add safety assert on sourceWidth

See commit 0d92eb65.
---
 src/main/scala/tile/VortexTile.scala | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/main/scala/tile/VortexTile.scala b/src/main/scala/tile/VortexTile.scala
index e74d888..c2a8b31 100644
--- a/src/main/scala/tile/VortexTile.scala
+++ b/src/main/scala/tile/VortexTile.scala
@@ -160,6 +160,10 @@ class VortexTile private (
     case Some(simtParam) => log2Ceil(simtParam.nSrcIds)
     case None => 4
   }
+  require(sourceWidth >= 4,
+    "Allocating a small number of sourceIds may cause correctness bug inside " +
+    "Vortex core due to unconstrained synchronization issues between warps." +
+    "We recommend setting nSrcIds to at least 16.")
 
   val imemNodes = Seq.tabulate(1) { i =>
     TLClientNode(Seq(TLMasterPortParameters.v1(