Store SizeEnum in entry instead of UInt
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@@ -13,7 +13,6 @@ import freechips.rocketchip.unittest._
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trait InFlightTableSizeEnum extends ChiselEnum {
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val INVALID: Type
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val FOUR: Type
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def logSizeToEnum(x: UInt): Type
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def enumToLogSize(x: Type): UInt
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}
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@@ -598,7 +597,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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numPerLaneReqs,
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sourceWidth,
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offsetBits,
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config.SizeEnum.getWidth
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config.SizeEnum
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)
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)
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println(s"=========== table sourceWidth: ${sourceWidth}")
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@@ -617,7 +616,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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r.valid := false.B
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r.source := origReqs(i).source
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r.offset := (origReqs(i).address % (1 << config.MAX_SIZE).U) >> config.WORD_WIDTH
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r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size).asUInt
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r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size)
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}
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}
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newEntry.lanes(0).reqs(0).valid := true.B
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@@ -753,7 +752,7 @@ class UncoalescingUnit(config: CoalescerConfig) extends Module {
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when(inflightTable.io.lookup.valid && oldReq.valid) {
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ioOldReq.valid := oldReq.valid
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ioOldReq.bits.source := oldReq.source
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val logSize = config.SizeEnum.enumToLogSize(config.SizeEnum(oldReq.sizeEnum))
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val logSize = found.sizeEnumT.enumToLogSize(oldReq.sizeEnum)
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ioOldReq.bits.size := logSize
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ioOldReq.bits.data :=
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getCoalescedDataChunk(
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@@ -780,7 +779,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
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config.DEPTH,
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log2Ceil(config.NUM_OLD_IDS),
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config.MAX_SIZE,
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config.SizeEnum.getWidth
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config.SizeEnum
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)
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val entries = config.NUM_NEW_IDS
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@@ -810,7 +809,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
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r.valid := false.B
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r.source := 0.U
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r.offset := 0.U
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r.sizeEnum := config.SizeEnum.INVALID.asUInt
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r.sizeEnum := config.SizeEnum.INVALID
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}
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}
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}
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@@ -858,14 +857,14 @@ class InflightCoalReqTableEntry(
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val numPerLaneReqs: Int,
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val sourceWidth: Int,
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val offsetBits: Int,
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val sizeEnumBits: Int
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val sizeEnumT: InFlightTableSizeEnum
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) extends Bundle {
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class PerCoreReq extends Bundle {
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val valid = Bool() // FIXME: delete this
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// FIXME: oldId and newId shares the same width
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val source = UInt(sourceWidth.W)
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val offset = UInt(offsetBits.W)
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val sizeEnum = UInt(sizeEnumBits.W)
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val sizeEnum = sizeEnumT()
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}
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class PerLane extends Bundle {
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val reqs = Vec(numPerLaneReqs, new PerCoreReq)
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