From 7539c39c45a81f7b531a9ef05a9a76db1311115d Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Sun, 23 Apr 2023 21:38:11 -0700
Subject: [PATCH] Store SizeEnum in entry instead of UInt

---
 src/main/scala/tilelink/Coalescing.scala          | 15 +++++++--------
 .../scala/coalescing/CoalescingUnitTest.scala     | 11 ++++++-----
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 2d3b118..826c749 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -13,7 +13,6 @@ import freechips.rocketchip.unittest._
 
 trait InFlightTableSizeEnum extends ChiselEnum {
   val INVALID: Type
-  val FOUR: Type
   def logSizeToEnum(x: UInt): Type
   def enumToLogSize(x: Type): UInt
 }
@@ -598,7 +597,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
       numPerLaneReqs,
       sourceWidth,
       offsetBits,
-      config.SizeEnum.getWidth
+      config.SizeEnum
     )
   )
   println(s"=========== table sourceWidth: ${sourceWidth}")
@@ -617,7 +616,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
       r.valid := false.B
       r.source := origReqs(i).source
       r.offset := (origReqs(i).address % (1 << config.MAX_SIZE).U) >> config.WORD_WIDTH
-      r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size).asUInt
+      r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size)
     }
   }
   newEntry.lanes(0).reqs(0).valid := true.B
@@ -753,7 +752,7 @@ class UncoalescingUnit(config: CoalescerConfig) extends Module {
       when(inflightTable.io.lookup.valid && oldReq.valid) {
         ioOldReq.valid := oldReq.valid
         ioOldReq.bits.source := oldReq.source
-        val logSize = config.SizeEnum.enumToLogSize(config.SizeEnum(oldReq.sizeEnum))
+        val logSize = found.sizeEnumT.enumToLogSize(oldReq.sizeEnum)
         ioOldReq.bits.size := logSize
         ioOldReq.bits.data :=
           getCoalescedDataChunk(
@@ -780,7 +779,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
     config.DEPTH,
     log2Ceil(config.NUM_OLD_IDS),
     config.MAX_SIZE,
-    config.SizeEnum.getWidth
+    config.SizeEnum
   )
 
   val entries = config.NUM_NEW_IDS
@@ -810,7 +809,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
           r.valid := false.B
           r.source := 0.U
           r.offset := 0.U
-          r.sizeEnum := config.SizeEnum.INVALID.asUInt
+          r.sizeEnum := config.SizeEnum.INVALID
         }
       }
     }
@@ -858,14 +857,14 @@ class InflightCoalReqTableEntry(
     val numPerLaneReqs: Int,
     val sourceWidth: Int,
     val offsetBits: Int,
-    val sizeEnumBits: Int
+    val sizeEnumT: InFlightTableSizeEnum
 ) extends Bundle {
   class PerCoreReq extends Bundle {
     val valid = Bool() // FIXME: delete this
     // FIXME: oldId and newId shares the same width
     val source = UInt(sourceWidth.W)
     val offset = UInt(offsetBits.W)
-    val sizeEnum = UInt(sizeEnumBits.W)
+    val sizeEnum = sizeEnumT()
   }
   class PerLane extends Bundle {
     val reqs = Vec(numPerLaneReqs, new PerCoreReq)
diff --git a/src/test/scala/coalescing/CoalescingUnitTest.scala b/src/test/scala/coalescing/CoalescingUnitTest.scala
index bf9a249..f1538ad 100644
--- a/src/test/scala/coalescing/CoalescingUnitTest.scala
+++ b/src/test/scala/coalescing/CoalescingUnitTest.scala
@@ -287,25 +287,26 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
     // .withAnnotations(Seq(VcsBackendAnnotation))
     { c =>
       val sourceId = 0.U
+      val four = c.io.newEntry.sizeEnumT.FOUR
       c.io.coalReqValid.poke(true.B)
       c.io.newEntry.source.poke(sourceId)
       c.io.newEntry.lanes(0).reqs(0).valid.poke(true.B)
       c.io.newEntry.lanes(0).reqs(0).source.poke(1.U)
       c.io.newEntry.lanes(0).reqs(0).offset.poke(1.U)
-      c.io.newEntry.lanes(0).reqs(0).sizeEnum.poke(1.U) // 1.U is FOUR
+      c.io.newEntry.lanes(0).reqs(0).sizeEnum.poke(four)
       c.io.newEntry.lanes(0).reqs(1).valid.poke(true.B)
       c.io.newEntry.lanes(0).reqs(1).source.poke(2.U)
       c.io.newEntry.lanes(0).reqs(1).offset.poke(0.U)
-      c.io.newEntry.lanes(0).reqs(1).sizeEnum.poke(1.U)
+      c.io.newEntry.lanes(0).reqs(1).sizeEnum.poke(four)
       c.io.newEntry.lanes(1).reqs(0).valid.poke(false.B)
       c.io.newEntry.lanes(2).reqs(0).valid.poke(true.B)
       c.io.newEntry.lanes(2).reqs(0).source.poke(2.U)
       c.io.newEntry.lanes(2).reqs(0).offset.poke(2.U)
-      c.io.newEntry.lanes(2).reqs(0).sizeEnum.poke(1.U)
+      c.io.newEntry.lanes(2).reqs(0).sizeEnum.poke(four)
       c.io.newEntry.lanes(2).reqs(1).valid.poke(true.B)
       c.io.newEntry.lanes(2).reqs(1).source.poke(2.U)
       c.io.newEntry.lanes(2).reqs(1).offset.poke(3.U)
-      c.io.newEntry.lanes(2).reqs(1).sizeEnum.poke(1.U)
+      c.io.newEntry.lanes(2).reqs(1).sizeEnum.poke(four)
       c.io.newEntry.lanes(3).reqs(0).valid.poke(false.B)
 
       c.clock.step()
@@ -350,7 +351,7 @@ class CoalInflightTableUnitTest extends AnyFlatSpec with ChiselScalatestTester {
   val sizeBits = 2
 
   val inflightCoalReqTableEntry =
-    new InflightCoalReqTableEntry(numLanes, numPerLaneReqs, sourceWidth, offsetBits, sizeBits)
+    new InflightCoalReqTableEntry(numLanes, numPerLaneReqs, sourceWidth, offsetBits, testConfig.SizeEnum)
 
   // it should "stop enqueueing when full" in {
   //   test(new InflightCoalReqTable(numLanes, sourceWidth, entries)) { c =>