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Parameterize barrier params better

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Some numbers still hardcoded at client side, need to do proper diplomacy
negotiation
This commit is contained in:
Hansung Kim
2024-03-21 13:21:13 -07:00
parent 0e9cb884a8
commit 7258d69ce8
3 changed files with 9 additions and 10 deletions
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2
src/main/scala/radiance/tile/RadianceCluster.scala
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@@ -98,8 +98,6 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp(
println(s"======= RadianceCluster: clbus name = ${outer.clbus.busName}") println(s"======= RadianceCluster: clbus name = ${outer.clbus.busName}")
} }
val numBarriers = 4 // FIXME: hardcoded
// @cleanup: This assumes barrier params on all edges are the same, i.e. all // @cleanup: This assumes barrier params on all edges are the same, i.e. all
// cores are configured to have the same barrier id range. While true, might // cores are configured to have the same barrier id range. While true, might
// be better to actually assert this // be better to actually assert this

6
src/main/scala/radiance/tile/RadianceTile.scala
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@@ -328,7 +328,11 @@ class RadianceTile private (
// Barrier synchronization node // Barrier synchronization node
// FIXME: hardcoded params // FIXME: hardcoded params
val barrierParams = BarrierParams(barrierIdBits = 2, numCoreBits = 1) val numBarriers = 8
val numCores = 2
def barrierIdBits = log2Ceil(numBarriers)
def coreIdBits = log2Ceil(numCores)
val barrierParams = BarrierParams(barrierIdBits = barrierIdBits, numCoreBits = coreIdBits)
val barrierMasterNode = BarrierMasterNode(barrierParams) val barrierMasterNode = BarrierMasterNode(barrierParams)
val base = p(GPUMemory()) match { val base = p(GPUMemory()) match {

11
src/main/scala/radiance/tile/VortexCore.scala
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@@ -90,15 +90,13 @@ class VortexBundle(tile: RadianceTile)(implicit p: Parameters) extends CoreBundl
val smem_d_ready = Output(UInt((tile.numLsuLanes * 1).W)) val smem_d_ready = Output(UInt((tile.numLsuLanes * 1).W))
// FIXME: hardcoded // FIXME: hardcoded
val NB_WIDTH = 2
val NC_WIDTH = 1
val gbar_req_valid = Output(Bool()) val gbar_req_valid = Output(Bool())
val gbar_req_id = Output(UInt(NB_WIDTH.W)) val gbar_req_id = Output(UInt(tile.barrierIdBits.W))
val gbar_req_size_m1 = Output(UInt(NC_WIDTH.W)) val gbar_req_size_m1 = Output(UInt(tile.coreIdBits.W))
val gbar_req_core_id = Output(UInt(NC_WIDTH.W)) val gbar_req_core_id = Output(UInt(tile.coreIdBits.W))
val gbar_req_ready = Input(Bool()) val gbar_req_ready = Input(Bool())
val gbar_rsp_valid = Input(Bool()) val gbar_rsp_valid = Input(Bool())
val gbar_rsp_id = Input(UInt(NB_WIDTH.W)) val gbar_rsp_id = Input(UInt(tile.barrierIdBits.W))
// val fpu = Flipped(new FPUCoreIO()) // val fpu = Flipped(new FPUCoreIO())
//val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) //val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
@@ -116,7 +114,6 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
// see VX_csr_data that implements the read logic for CSR_MHARTID/GWID. // see VX_csr_data that implements the read logic for CSR_MHARTID/GWID.
Map( Map(
"CORE_ID" -> tile.tileParams.tileId, "CORE_ID" -> tile.tileParams.tileId,
"CORES_PER_CLUSTER" -> 2, // FIXME: hardcoded
// TODO: can we get this as a parameter? // TODO: can we get this as a parameter?
"BOOTROM_HANG100" -> 0x10100, "BOOTROM_HANG100" -> 0x10100,
"NUM_THREADS" -> tile.numLsuLanes "NUM_THREADS" -> tile.numLsuLanes