diff --git a/src/main/scala/radiance/tile/RadianceCluster.scala b/src/main/scala/radiance/tile/RadianceCluster.scala
index 208039e..f45607f 100644
--- a/src/main/scala/radiance/tile/RadianceCluster.scala
+++ b/src/main/scala/radiance/tile/RadianceCluster.scala
@@ -98,8 +98,6 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp(
     println(s"======= RadianceCluster: clbus name = ${outer.clbus.busName}")
   }
 
-  val numBarriers = 4 // FIXME: hardcoded
-
   // @cleanup: This assumes barrier params on all edges are the same, i.e. all
   // cores are configured to have the same barrier id range.  While true, might
   // be better to actually assert this
diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala
index 59c6fed..7d323ee 100644
--- a/src/main/scala/radiance/tile/RadianceTile.scala
+++ b/src/main/scala/radiance/tile/RadianceTile.scala
@@ -328,7 +328,11 @@ class RadianceTile private (
 
   // Barrier synchronization node
   // FIXME: hardcoded params
-  val barrierParams = BarrierParams(barrierIdBits = 2, numCoreBits = 1)
+  val numBarriers = 8
+  val numCores = 2
+  def barrierIdBits = log2Ceil(numBarriers)
+  def coreIdBits = log2Ceil(numCores)
+  val barrierParams = BarrierParams(barrierIdBits = barrierIdBits, numCoreBits = coreIdBits)
   val barrierMasterNode = BarrierMasterNode(barrierParams)
 
   val base = p(GPUMemory()) match {
diff --git a/src/main/scala/radiance/tile/VortexCore.scala b/src/main/scala/radiance/tile/VortexCore.scala
index 7a06f7d..b9634aa 100644
--- a/src/main/scala/radiance/tile/VortexCore.scala
+++ b/src/main/scala/radiance/tile/VortexCore.scala
@@ -90,15 +90,13 @@ class VortexBundle(tile: RadianceTile)(implicit p: Parameters) extends CoreBundl
   val smem_d_ready = Output(UInt((tile.numLsuLanes * 1).W))
 
   // FIXME: hardcoded
-  val NB_WIDTH = 2
-  val NC_WIDTH = 1
   val gbar_req_valid = Output(Bool())
-  val gbar_req_id = Output(UInt(NB_WIDTH.W))
-  val gbar_req_size_m1 = Output(UInt(NC_WIDTH.W))
-  val gbar_req_core_id = Output(UInt(NC_WIDTH.W))
+  val gbar_req_id = Output(UInt(tile.barrierIdBits.W))
+  val gbar_req_size_m1 = Output(UInt(tile.coreIdBits.W))
+  val gbar_req_core_id = Output(UInt(tile.coreIdBits.W))
   val gbar_req_ready = Input(Bool())
   val gbar_rsp_valid = Input(Bool())
-  val gbar_rsp_id = Input(UInt(NB_WIDTH.W))
+  val gbar_rsp_id = Input(UInt(tile.barrierIdBits.W))
 
   // val fpu = Flipped(new FPUCoreIO())
   //val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
@@ -116,7 +114,6 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
       // see VX_csr_data that implements the read logic for CSR_MHARTID/GWID.
       Map(
         "CORE_ID" -> tile.tileParams.tileId,
-        "CORES_PER_CLUSTER" -> 2, // FIXME: hardcoded
         // TODO: can we get this as a parameter?
         "BOOTROM_HANG100" -> 0x10100,
         "NUM_THREADS" -> tile.numLsuLanes