Revert SimMemTrace.v to use posedge clock

Doing function calls inside @(*) causes lint errors.  Instead, remove
staging registers to eliminate 1 cycle latency between DPI call and
when output is visible to Chisel.

src/main/resources/vsrc/SimMemTrace.v

@@ -39,49 +39,32 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) (
   output [`DATA_WIDTH*NUM_LANES-1:0]    trace_read_data,
   output                                trace_read_finished
 );
-  bit     __in_valid   [NUM_LANES-1:0];
+  bit                      __in_valid   [NUM_LANES-1:0];
-  longint __in_address [NUM_LANES-1:0];
+  longint                  __in_address [NUM_LANES-1:0];
-
+  bit                      __in_is_store [NUM_LANES-1:0];
-  bit     __in_is_store [NUM_LANES-1:0];
   reg [`LOGSIZE_WIDTH-1:0] __in_size [NUM_LANES-1:0];
-  longint __in_data [NUM_LANES-1:0];
+  longint                  __in_data [NUM_LANES-1:0];
-
+  bit                      __in_finished;
-  bit __in_finished;
-  string __uartlog;
-
-  // Cycle counter that is used to query C parser whether we have a request
-  // coming in at the current cycle.
-
-
-  // registers that stage outputs of the C parser
-  reg [NUM_LANES-1:0]   __in_valid_wire;
-  reg [`DATA_WIDTH-1:0] __in_address_wire [NUM_LANES-1:0];
-
-  reg [NUM_LANES-1:0]      __in_is_store_wire;
-  reg [`LOGSIZE_WIDTH-1:0] __in_size_wire [NUM_LANES-1:0];
-  reg [`DATA_WIDTH-1:0]    __in_data_wire [NUM_LANES-1:0];
-  reg                      __in_finished_wire;
 
   genvar g;
-
   generate
     for (g = 0; g < NUM_LANES; g = g + 1) begin
-      assign trace_read_valid[g] = __in_valid_wire[g];
+      assign trace_read_valid[g] = __in_valid[g];
-      assign trace_read_address[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g]  = __in_address_wire[g];
+      assign trace_read_address[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g]  = __in_address[g];
 
-      assign trace_read_is_store[g] = __in_is_store_wire[g];
+      assign trace_read_is_store[g] = __in_is_store[g];
-      assign trace_read_size[`LOGSIZE_WIDTH*(g+1)-1:`LOGSIZE_WIDTH*g] = __in_size_wire[g];
+      assign trace_read_size[`LOGSIZE_WIDTH*(g+1)-1:`LOGSIZE_WIDTH*g] = __in_size[g];
-      assign trace_read_data[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g] = __in_data_wire[g];
+      assign trace_read_data[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g] = __in_data[g];
     end
   endgenerate
-  assign trace_read_finished = __in_finished_wire;
+  assign trace_read_finished = __in_finished;
 
   initial begin
       /* $value$plusargs("uartlog=%s", __uartlog); */
       memtrace_init(FILENAME);
   end
 
-  always @(*) begin
+  always @(posedge clock) begin
     if (reset) begin
       for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
         __in_valid[tid] = 1'b0;
@@ -91,32 +74,12 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) (
         __in_size[tid] = `LOGSIZE_WIDTH'b0;
         __in_data[tid] = `DATA_WIDTH'b0;
       end
-
       __in_finished = 1'b0;
-
-      //cycle_counter <= `DATA_WIDTH'b0;
-
-      // setting default value for register to avoid latches
-      for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
-        __in_valid_wire[tid] = 1'b0;
-        __in_address_wire[tid] = `DATA_WIDTH'b0;
-
-        __in_is_store_wire[tid] = 1'b0;
-        __in_size_wire[tid] = `LOGSIZE_WIDTH'b0;
-        __in_data_wire[tid] = `DATA_WIDTH'b0;
-      end
-
-      __in_finished_wire = 1'b0;
     end else begin
-
-      // Getting values from C function into pseudeo register
       for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
         memtrace_query(
           trace_read_ready,
-          // Since parsed results are latched to the output on the next
+          trace_read_cycle,
-          // cycle due to staging registers, we need to pass in the next cycle
-          // to sync up.
-          trace_read_cycle,  // the left replace next_cycle_counter,
           tid,
 
           __in_valid[tid],
@@ -129,17 +92,6 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) (
           __in_finished
         );
       end
-
-      // Connect values from pseudo register into verilog register 
-      for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
-        __in_valid_wire[tid]   = __in_valid[tid];
-        __in_address_wire[tid] = __in_address[tid];
-
-        __in_is_store_wire[tid] = __in_is_store[tid];
-        __in_size_wire[tid] = __in_size[tid];
-        __in_data_wire[tid] = __in_data[tid];
-      end
-      __in_finished_wire = __in_finished;
     end
   end
 endmodule