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fix unaligned port

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This commit is contained in:
Richard Yan
2024-10-24 13:42:45 -07:00
parent 9b8d16d184
commit 68e715e284
1 changed files with 4 additions and 2 deletions
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6
src/main/scala/radiance/tile/VirgoSharedMemComponents.scala
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@@ -130,11 +130,13 @@ class VirgoSharedMemComponents(
val filterNode = AlignFilterNode(Seq(address))(p, ValName(s"filter_l${lid}_w${wid}")) val filterNode = AlignFilterNode(Seq(address))(p, ValName(s"filter_l${lid}_w${wid}"))
DisableMonitors { implicit p => filterNode := lane } DisableMonitors { implicit p => filterNode := lane }
val alignedSplitter = Seq(connectOne(filterNode, () =>
RWSplitterNode(address, s"aligned_splitter_c${cid}_l${lid}_w${wid}")))
unalignedRWNodes(lid)(cid) = connectOne(filterNode, () => unalignedRWNodes(lid)(cid) = connectOne(filterNode, () =>
RWSplitterNode(AddressSet.everything, s"unaligned_splitter_c${cid}_l${lid}")) RWSplitterNode(AddressSet.everything, s"unaligned_splitter_c${cid}_l${lid}"))
Seq(connectOne(filterNode, () => alignedSplitter
RWSplitterNode(address, s"aligned_splitter_c${cid}_l${lid}_w${wid}")))
} else Seq() } else Seq()
} }
} }