From 68e715e284b057da9b8423c8b3e6ebe4aeee30aa Mon Sep 17 00:00:00 2001
From: Richard Yan <yrh@berkeley.edu>
Date: Thu, 24 Oct 2024 13:42:45 -0700
Subject: [PATCH] fix unaligned port

---
 src/main/scala/radiance/tile/VirgoSharedMemComponents.scala | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/radiance/tile/VirgoSharedMemComponents.scala b/src/main/scala/radiance/tile/VirgoSharedMemComponents.scala
index ae143eb..5e666cf 100644
--- a/src/main/scala/radiance/tile/VirgoSharedMemComponents.scala
+++ b/src/main/scala/radiance/tile/VirgoSharedMemComponents.scala
@@ -130,11 +130,13 @@ class VirgoSharedMemComponents(
                 val filterNode = AlignFilterNode(Seq(address))(p, ValName(s"filter_l${lid}_w${wid}"))
                 DisableMonitors { implicit p => filterNode := lane }
 
+                val alignedSplitter = Seq(connectOne(filterNode, () =>
+                  RWSplitterNode(address, s"aligned_splitter_c${cid}_l${lid}_w${wid}")))
+
                 unalignedRWNodes(lid)(cid) = connectOne(filterNode, () =>
                   RWSplitterNode(AddressSet.everything, s"unaligned_splitter_c${cid}_l${lid}"))
 
-                Seq(connectOne(filterNode, () =>
-                  RWSplitterNode(address, s"aligned_splitter_c${cid}_l${lid}_w${wid}")))
+                alignedSplitter
               } else Seq()
             }
           }