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Change dcache sourceWidth constant to match DCACHE_NOSM_TAG_WIDTH

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Hansung Kim
2023-11-17 19:12:03 -08:00
parent 05ffa884a6
commit 6802d23598
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/rocket/VortexCore.scala
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@@ -46,8 +46,8 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 46, dataWidth = 32))) val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 46, dataWidth = 32)))
})) else None })) else None
val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle { val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle {
val a = Decoupled(new VortexBundleA(sourceWidth = 47, dataWidth = 32)) val a = Decoupled(new VortexBundleA(sourceWidth = 46, dataWidth = 32))
val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 47, dataWidth = 32))) val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 46, dataWidth = 32)))
})) else None })) else None
val mem = if (tile.vortexParams.useVxCache) Some(new Bundle { val mem = if (tile.vortexParams.useVxCache) Some(new Bundle {
val a = Decoupled(new VortexBundleA(sourceWidth = 15, dataWidth = 128)) val a = Decoupled(new VortexBundleA(sourceWidth = 15, dataWidth = 128))
@@ -163,6 +163,7 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
addResource("/vsrc/vortex/hw/rtl/mem/VX_shared_mem.sv") addResource("/vsrc/vortex/hw/rtl/mem/VX_shared_mem.sv")
addResource("/vsrc/vortex/hw/rtl/mem/VX_smem_switch.sv") addResource("/vsrc/vortex/hw/rtl/mem/VX_smem_switch.sv")
// tex_unit missing in Vortex 2.0 // tex_unit missing in Vortex 2.0
// addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv") // addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv")
// addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_stride.sv") // addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_stride.sv")