diff --git a/src/main/scala/rocket/VortexCore.scala b/src/main/scala/rocket/VortexCore.scala
index a82b631..daac52f 100644
--- a/src/main/scala/rocket/VortexCore.scala
+++ b/src/main/scala/rocket/VortexCore.scala
@@ -46,8 +46,8 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
     val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 46, dataWidth = 32)))
   })) else None
   val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle {
-    val a = Decoupled(new VortexBundleA(sourceWidth = 47, dataWidth = 32))
-    val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 47, dataWidth = 32)))
+    val a = Decoupled(new VortexBundleA(sourceWidth = 46, dataWidth = 32))
+    val d = Flipped(Decoupled(new VortexBundleD(sourceWidth = 46, dataWidth = 32)))
   })) else None
   val mem = if (tile.vortexParams.useVxCache) Some(new Bundle { 
     val a = Decoupled(new VortexBundleA(sourceWidth = 15, dataWidth = 128))
@@ -163,6 +163,7 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   addResource("/vsrc/vortex/hw/rtl/mem/VX_shared_mem.sv")
   addResource("/vsrc/vortex/hw/rtl/mem/VX_smem_switch.sv")
 
+
   // tex_unit missing in Vortex 2.0
   // addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv")
   // addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_stride.sv")