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Pass hang100 address to wrapper verilog

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This commit is contained in:
Hansung Kim
2023-11-16 18:00:40 -08:00
parent dca74eface
commit 65f4264d57
1 changed files with 5 additions and 2 deletions
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7
src/main/scala/rocket/VortexCore.scala
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@@ -70,7 +70,11 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
// Each Vortex core gets tied-off hartId of 0, 1, 2, 3, ... // Each Vortex core gets tied-off hartId of 0, 1, 2, 3, ...
// The actual MHARTID read by the program is different by warp, not core; // The actual MHARTID read by the program is different by warp, not core;
// see VX_csr_data that implements the read logic for CSR_MHARTID/GWID. // see VX_csr_data that implements the read logic for CSR_MHARTID/GWID.
Map("CORE_ID" -> tile.tileParams.hartId) Map(
"CORE_ID" -> tile.tileParams.hartId,
// TODO: can we get this as a parameter?
"BOOTROM_HANG100" -> 0x10100,
)
) )
with HasBlackBoxResource { with HasBlackBoxResource {
// addResource("/vsrc/vortex/hw/unit_tests/generic_queue/testbench.v") // addResource("/vsrc/vortex/hw/unit_tests/generic_queue/testbench.v")
@@ -159,7 +163,6 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
addResource("/vsrc/vortex/hw/rtl/mem/VX_shared_mem.sv") addResource("/vsrc/vortex/hw/rtl/mem/VX_shared_mem.sv")
addResource("/vsrc/vortex/hw/rtl/mem/VX_smem_switch.sv") addResource("/vsrc/vortex/hw/rtl/mem/VX_smem_switch.sv")
// tex_unit missing in Vortex 2.0 // tex_unit missing in Vortex 2.0
// addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv") // addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv")
// addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_stride.sv") // addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_stride.sv")