From 65f4264d5728ba84f6ea00abe869d71cbda85183 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Thu, 16 Nov 2023 18:00:40 -0800 Subject: [PATCH] Pass hang100 address to wrapper verilog --- src/main/scala/rocket/VortexCore.scala | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/VortexCore.scala b/src/main/scala/rocket/VortexCore.scala index 2c13e61..a82b631 100644 --- a/src/main/scala/rocket/VortexCore.scala +++ b/src/main/scala/rocket/VortexCore.scala @@ -70,7 +70,11 @@ class Vortex(tile: VortexTile)(implicit p: Parameters) // Each Vortex core gets tied-off hartId of 0, 1, 2, 3, ... // The actual MHARTID read by the program is different by warp, not core; // see VX_csr_data that implements the read logic for CSR_MHARTID/GWID. - Map("CORE_ID" -> tile.tileParams.hartId) + Map( + "CORE_ID" -> tile.tileParams.hartId, + // TODO: can we get this as a parameter? + "BOOTROM_HANG100" -> 0x10100, + ) ) with HasBlackBoxResource { // addResource("/vsrc/vortex/hw/unit_tests/generic_queue/testbench.v") @@ -159,7 +163,6 @@ class Vortex(tile: VortexTile)(implicit p: Parameters) addResource("/vsrc/vortex/hw/rtl/mem/VX_shared_mem.sv") addResource("/vsrc/vortex/hw/rtl/mem/VX_smem_switch.sv") - // tex_unit missing in Vortex 2.0 // addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv") // addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_stride.sv")