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Enable memtrace logger in SoC config

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This commit is contained in:
Hansung Kim
2023-05-14 19:21:08 -07:00
parent e7b3455127
commit 64de77d350
1 changed files with 12 additions and 3 deletions
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15
src/main/scala/tilelink/TracerSystemMem.scala
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@@ -13,8 +13,16 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
// Safe to use get as WithMemtraceCore requires WithNLanes to be defined
val simtParam = p(SIMTCoreKey).get
val config = defaultConfig.copy(numLanes = simtParam.nLanes)
val numLanes = simtParam.nLanes
val filename = param.tracefilename
val tracer = LazyModule(
new MemTraceDriver(config, param.tracefilename, param.traceHasSource)(p)
new MemTraceDriver(config, filename, param.traceHasSource)(p)
)
val coreSideLogger = LazyModule(
new MemTraceLogger(numLanes, filename, loggerName = "coreside")
)
val memSideLogger = LazyModule(
new MemTraceLogger(numLanes + 1, filename, loggerName = "memside")
)
// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
// when connecting to SBus
@@ -25,8 +33,9 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
case Some(coalParam) => {
val coal = LazyModule(new CoalescingUnit(coalParam))
println(s"============ CoalescingUnit instantiated [numLanes=${coalParam.numLanes}]")
coal.cpuNode :=* tracer.node // N lanes
coal.aggregateNode // N+1 lanes
coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
memSideLogger.node :=* coal.aggregateNode // N+1 lanes
memSideLogger.node
}
case None => tracer.node
}