diff --git a/src/main/scala/tilelink/TracerSystemMem.scala b/src/main/scala/tilelink/TracerSystemMem.scala
index f699eeb..02dcd94 100644
--- a/src/main/scala/tilelink/TracerSystemMem.scala
+++ b/src/main/scala/tilelink/TracerSystemMem.scala
@@ -13,8 +13,16 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
     // Safe to use get as WithMemtraceCore requires WithNLanes to be defined
     val simtParam = p(SIMTCoreKey).get
     val config = defaultConfig.copy(numLanes = simtParam.nLanes)
+    val numLanes = simtParam.nLanes
+    val filename = param.tracefilename
     val tracer = LazyModule(
-      new MemTraceDriver(config, param.tracefilename, param.traceHasSource)(p)
+      new MemTraceDriver(config, filename, param.traceHasSource)(p)
+    )
+    val coreSideLogger = LazyModule(
+      new MemTraceLogger(numLanes, filename, loggerName = "coreside")
+    )
+    val memSideLogger = LazyModule(
+      new MemTraceLogger(numLanes + 1, filename, loggerName = "memside")
     )
     // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
     // when connecting to SBus
@@ -25,8 +33,9 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
       case Some(coalParam) => {
         val coal = LazyModule(new CoalescingUnit(coalParam))
         println(s"============ CoalescingUnit instantiated [numLanes=${coalParam.numLanes}]")
-        coal.cpuNode :=* tracer.node // N lanes
-        coal.aggregateNode           // N+1 lanes
+        coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
+        memSideLogger.node :=* coal.aggregateNode            // N+1 lanes
+        memSideLogger.node
       }
       case None => tracer.node
     }