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Allow trace driver to make double-word reqs

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This is mostly for testing purposes.
This commit is contained in:
Hansung Kim
2023-04-23 12:23:10 -07:00
parent a7baf57e49
commit 4d16ec9b08
1 changed files with 8 additions and 12 deletions
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20
src/main/scala/tilelink/Coalescing.scala
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@@ -552,15 +552,16 @@ class UncoalescingUnit(config: CoalescerConfig, tlCoalD: TLBundleD) extends Modu
(dataWidth > 0).B && (dataWidth.U % sizeInBits === 0.U), (dataWidth > 0).B && (dataWidth.U % sizeInBits === 0.U),
s"coalesced data width ($dataWidth) not evenly divisible by core req size ($sizeInBits)" s"coalesced data width ($dataWidth) not evenly divisible by core req size ($sizeInBits)"
) )
assert(logSize === 2.U || logSize === 0.U, "TODO: currently only supporting 4-byte accesses") assert(logSize === 2.U, "currently only supporting 4-byte accesses. TODO")
val numChunks = dataWidth / 32 val numChunks = dataWidth / 32
val chunks = Wire(Vec(numChunks, UInt(32.W))) val chunks = Wire(Vec(numChunks, UInt(32.W)))
val offsets = (0 until numChunks) val offsets = (0 until numChunks)
(chunks zip offsets).foreach { case (c, o) => (chunks zip offsets).foreach { case (c, o) =>
// Take [(off+1)*size-1:off*size] starting from LSB // FIXME: whether to take the offset from MSB or LSB depends on
// FIXME: whether to take the offset from MSB or LSB depends on endianness // endianness. Right now we're assuming little endian
c := data(32 * (o + 1) - 1, 32 * o) c := data(32 * (o + 1) - 1, 32 * o)
// c := (data >> (dataWidth - (o + 1) * 32)) & sizeMask // If taking from MSB:
// c := (data >> (dataWidth - (o + 1) * 32)) & sizeMask
} }
chunks(offset) // MUX chunks(offset) // MUX
} }
@@ -667,7 +668,6 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
} }
class InflightCoalReqTableEntry( class InflightCoalReqTableEntry(
val numLanes: Int, val numLanes: Int,
// Maximum number of requests from a single lane that can get coalesced into a single request // Maximum number of requests from a single lane that can get coalesced into a single request
val numPerLaneReqs: Int, val numPerLaneReqs: Int,
@@ -799,19 +799,15 @@ class MemTraceDriverImp(outer: MemTraceDriver, config: CoalescerConfig, traceFil
val offsetInWord = req.address % config.WORD_SIZE.U val offsetInWord = req.address % config.WORD_SIZE.U
val subword = req.size < log2Ceil(config.WORD_SIZE).U val subword = req.size < log2Ceil(config.WORD_SIZE).U
// `mask` is currently unused
val mask = Wire(UInt(config.WORD_SIZE.W)) val mask = Wire(UInt(config.WORD_SIZE.W))
val wordData = Wire(UInt((config.WORD_SIZE * 8).W)) val wordData = Wire(UInt((config.WORD_SIZE * 8 * 2).W))
val sizeInBytes = Wire(UInt((sizeW + 1).W)) val sizeInBytes = Wire(UInt((sizeW + 1).W))
sizeInBytes := (1.U) << req.size sizeInBytes := (1.U) << req.size
mask := Mux(subword, (~((~0.U(64.W)) << sizeInBytes)) << offsetInWord, ~0.U) mask := Mux(subword, (~((~0.U(64.W)) << sizeInBytes)) << offsetInWord, ~0.U)
wordData := Mux(subword, req.data << (offsetInWord * 8.U), req.data) wordData := Mux(subword, req.data << (offsetInWord * 8.U), req.data)
val wordAlignedAddress = req.address & ~((1 << log2Ceil(config.WORD_SIZE)) - 1).U(addrW.W) val wordAlignedAddress = req.address & ~((1 << log2Ceil(config.WORD_SIZE)) - 1).U(addrW.W)
val wordAlignedSize = Mux(subword, 2.U, req.size)
assert(
req.size <= log2Ceil(config.WORD_SIZE).U,
s"trace driver currently does not support access sizes larger than word size (${config.WORD_SIZE})"
)
val wordAlignedSize = 2.U // FIXME: hardcoded
// when(req.valid && subword) { // when(req.valid && subword) {
// printf( // printf(