From 4d16ec9b08a1799383177ef43bb30be17ddb8849 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Sun, 23 Apr 2023 12:23:10 -0700
Subject: [PATCH] Allow trace driver to make double-word reqs

This is mostly for testing purposes.
---
 src/main/scala/tilelink/Coalescing.scala | 20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 53ad832..1c6d0d3 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -552,15 +552,16 @@ class UncoalescingUnit(config: CoalescerConfig, tlCoalD: TLBundleD) extends Modu
       (dataWidth > 0).B && (dataWidth.U % sizeInBits === 0.U),
       s"coalesced data width ($dataWidth) not evenly divisible by core req size ($sizeInBits)"
     )
-    assert(logSize === 2.U || logSize === 0.U, "TODO: currently only supporting 4-byte accesses")
+    assert(logSize === 2.U, "currently only supporting 4-byte accesses. TODO")
     val numChunks = dataWidth / 32
     val chunks = Wire(Vec(numChunks, UInt(32.W)))
     val offsets = (0 until numChunks)
     (chunks zip offsets).foreach { case (c, o) =>
-      // Take [(off+1)*size-1:off*size] starting from LSB
-      // FIXME: whether to take the offset from MSB or LSB depends on endianness
+      // FIXME: whether to take the offset from MSB or LSB depends on
+      // endianness.  Right now we're assuming little endian
       c := data(32 * (o + 1) - 1, 32 * o)
-    // c := (data >> (dataWidth - (o + 1) * 32)) & sizeMask
+      // If taking from MSB:
+      // c := (data >> (dataWidth - (o + 1) * 32)) & sizeMask
     }
     chunks(offset) // MUX
   }
@@ -667,7 +668,6 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
 }
 
 class InflightCoalReqTableEntry(
-
     val numLanes: Int,
     // Maximum number of requests from a single lane that can get coalesced into a single request
     val numPerLaneReqs: Int,
@@ -799,19 +799,15 @@ class MemTraceDriverImp(outer: MemTraceDriver, config: CoalescerConfig, traceFil
     val offsetInWord = req.address % config.WORD_SIZE.U
     val subword = req.size < log2Ceil(config.WORD_SIZE).U
 
+    // `mask` is currently unused
     val mask = Wire(UInt(config.WORD_SIZE.W))
-    val wordData = Wire(UInt((config.WORD_SIZE * 8).W))
+    val wordData = Wire(UInt((config.WORD_SIZE * 8 * 2).W))
     val sizeInBytes = Wire(UInt((sizeW + 1).W))
     sizeInBytes := (1.U) << req.size
     mask := Mux(subword, (~((~0.U(64.W)) << sizeInBytes)) << offsetInWord, ~0.U)
     wordData := Mux(subword, req.data << (offsetInWord * 8.U), req.data)
     val wordAlignedAddress = req.address & ~((1 << log2Ceil(config.WORD_SIZE)) - 1).U(addrW.W)
-
-    assert(
-      req.size <= log2Ceil(config.WORD_SIZE).U,
-      s"trace driver currently does not support access sizes larger than word size (${config.WORD_SIZE})"
-    )
-    val wordAlignedSize = 2.U // FIXME: hardcoded
+    val wordAlignedSize = Mux(subword, 2.U, req.size)
 
     // when(req.valid && subword) {
     //   printf(