wu-arch/radiance
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Generate proper AccessAck/AccessAckData from response queue

Browse Source
This commit is contained in:
Hansung Kim
2023-04-21 16:14:18 -07:00
parent e04ffe2130
commit 3f9f7a1d67
2 changed files with 9 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/resources/csrc/SimMemTraceLogger.cc
View File

@@ -88,8 +88,8 @@ extern "C" void memtracelogger_log(int handle,
return; return;
} }
printf("%s: [%lu] valid: address=%lx, tid=%u, size=%d\n", __func__, // printf("%s: [%lu] valid: address=%lx, tid=%u, size=%d\n", __func__,
trace_log_cycle, trace_log_address, trace_log_lane_id, trace_log_size); // trace_log_cycle, trace_log_address, trace_log_lane_id, trace_log_size);
MemTraceLine line{.valid = (trace_log_valid == 1), MemTraceLine line{.valid = (trace_log_valid == 1),
.cycle = static_cast<long>(trace_log_cycle), .cycle = static_cast<long>(trace_log_cycle),

10
src/main/scala/tilelink/Coalescing.scala
View File

@@ -193,12 +193,16 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
tlIn.d.valid := respQueue.io.deq(respQueueNoncoalPort).valid tlIn.d.valid := respQueue.io.deq(respQueueNoncoalPort).valid
val respHead = respQueue.io.deq(respQueueNoncoalPort).bits val respHead = respQueue.io.deq(respQueueNoncoalPort).bits
// TODO: AccessAckData for Get val apBits = edgeIn.AccessAck(
val respBits = edgeIn.AccessAck(
toSource = respHead.source, toSource = respHead.source,
lgSize = 0.U, lgSize = respHead.size
)
val agBits = edgeIn.AccessAck(
toSource = respHead.source,
lgSize = respHead.size,
data = respHead.data data = respHead.data
) )
val respBits = Mux(respHead.isStore, apBits, agBits)
tlIn.d.bits := respBits tlIn.d.bits := respBits
// Debug only // Debug only