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Generate proper AccessAck/AccessAckData from response queue

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This commit is contained in:
Hansung Kim
2023-04-21 16:14:18 -07:00
parent e04ffe2130
commit 3f9f7a1d67
2 changed files with 9 additions and 5 deletions
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10
src/main/scala/tilelink/Coalescing.scala
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@@ -193,12 +193,16 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
tlIn.d.valid := respQueue.io.deq(respQueueNoncoalPort).valid
val respHead = respQueue.io.deq(respQueueNoncoalPort).bits
// TODO: AccessAckData for Get
val respBits = edgeIn.AccessAck(
val apBits = edgeIn.AccessAck(
toSource = respHead.source,
lgSize = 0.U,
lgSize = respHead.size
)
val agBits = edgeIn.AccessAck(
toSource = respHead.source,
lgSize = respHead.size,
data = respHead.data
)
val respBits = Mux(respHead.isStore, apBits, agBits)
tlIn.d.bits := respBits
// Debug only