Test with Get() and doc source ID allocation
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@@ -55,19 +55,22 @@ class CoalescingUnit(numThreads: Int = 1)(implicit p: Parameters)
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// out.a.bits.data := 0xFF.U
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// out.a.bits.data := 0xFF.U
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// dontTouch(out.a.bits.data)
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// dontTouch(out.a.bits.data)
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tlOut.a.bits := edgeOut
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tlOut.a.bits := edgeOut
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.Put(
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.Get(
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// FIXME: When using TLRAM, unlike TLTestRAM, D requests do not come
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// around immediately, so need to keep track of inflight requests and
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// allocate sourceId accordingly.
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fromSource = 0.U,
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fromSource = 0.U,
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toAddress = 0.U,
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toAddress = tlIn.a.bits.data, // should be aligned to 2**lgSize
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// 64 bits = 8 bytes = 2**(3) bytes
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// 64 bits = 8 bytes = 2**(3) bytes
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lgSize = 3.U,
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lgSize = 0.U,
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// data = (i + 100).U
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// data = (i + 100).U
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data = tlIn.a.bits.data + 0xFF.U
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// data = tlIn.a.bits.data + 0xFF.U
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)
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)
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._2
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._2
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tlIn.d <> tlOut.d
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tlIn.d <> tlOut.d
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}
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node.out.foreach { case (tl, _) =>
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dontTouch(tlOut.a)
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dontTouch(tl.a)
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dontTouch(tlOut.d)
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}
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}
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val (tlCoal, _) = coalescerNode.out(0)
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val (tlCoal, _) = coalescerNode.out(0)
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dontTouch(tlCoal.a)
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dontTouch(tlCoal.a)
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