From 337272764b389e2beb1e4400b6e56353d5b6429b Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 6 Mar 2023 23:15:30 -0800 Subject: [PATCH] Test with Get() and doc source ID allocation --- src/main/scala/tilelink/Coalescing.scala | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 743c67f..db364a7 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -55,19 +55,22 @@ class CoalescingUnit(numThreads: Int = 1)(implicit p: Parameters) // out.a.bits.data := 0xFF.U // dontTouch(out.a.bits.data) tlOut.a.bits := edgeOut - .Put( + .Get( + // FIXME: When using TLRAM, unlike TLTestRAM, D requests do not come + // around immediately, so need to keep track of inflight requests and + // allocate sourceId accordingly. fromSource = 0.U, - toAddress = 0.U, + toAddress = tlIn.a.bits.data, // should be aligned to 2**lgSize // 64 bits = 8 bytes = 2**(3) bytes - lgSize = 3.U, + lgSize = 0.U, // data = (i + 100).U - data = tlIn.a.bits.data + 0xFF.U + // data = tlIn.a.bits.data + 0xFF.U ) ._2 tlIn.d <> tlOut.d - } - node.out.foreach { case (tl, _) => - dontTouch(tl.a) + + dontTouch(tlOut.a) + dontTouch(tlOut.d) } val (tlCoal, _) = coalescerNode.out(0) dontTouch(tlCoal.a)